EVAL-ADM1075EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-ADM1075EBZ
Analog Devices
'EVAL-ADM1075EBZ' PDF : 52 Pages View PDF
Data Sheet
ADM1075
the PLIM pin, the relationship of VDS to VPLIM can be controlled.
The foldback voltage, VFLB, is the input to the current limit
reference selector block and is defined as
VFLB = 0.1/VPLIM
The resistor divider should be designed to generate a VFLB
voltage equal to ISET when the VDS of the FET (and thus VPLIM)
rises above the desired power level. If ISET = 1 V, VPLIM needs to
be 0.1 V at the point where constant power takes over (VFLB =
ISET). For example, to generate a 200 W constant power limit at
10 A current limit, the maximum VDS is required to be 20 V at
the current limit. Therefore, the resistor divider must be 200:1
to generate a 0.1 V PLIM voltage at VDS = 20 V. As VPLIM
continues to increase, the current limit reference follows VFLB
because it is now the lowest voltage input to the current limit
reference selector block. This results in a reduction of the
current limit, and, therefore, the regulated load current. To
prevent complete current flow restriction, a clamp becomes
active when the current limit reference reaches 100 mV. The
current limit cannot drop below this level. This 200 W constant
power example is illustrated in terms of FET SOA and real
scope plots in Figure 49 and Figure 50.
When VFLB has control of the current limit reference, the
regulation current through the FET is
ID = VFLB/(Gain × RSENSE)
1000
100
10
1
0.1
0.1
1µs
10µs
100µs
1ms
MAX 200W
POWER
DISSIPATION
10ms
20V × 10A = 200W
DC
60V × 3.33A = 200W
1
10
100
VDS (V)
Figure 49. FET SOA
1000
CURRENT LIMIT ADJUSTING
GATE
IIN
3,4
VIN
VDS 200W CONSTANT POWER
where ID is the external FET drain current, and Gain is the sense
amplifier gain.
ID = 0.1/(VPLIM × Gain × RSENSE)
ID = 0.1/(VDS × D × Gain × RSENSE)
where D is the resistor divider factor on PLIM.
Therefore, the FET power is calculated as
PFET = ID × VDS = 0.1/(D × Gain × RSENSE)
Because PFET does not have any dependency on VDS, it remains
constant. Therefore, the FET power for a given system can be
set by adjusting the divider (D) driving the PLIM pin.
The limits to the constant power system are when VFLB > ISET (or
1 V if VISET > V ) ISETRSTH or when VFLB < 100 mV (100 mV max
clamp on VCLREF). With an ISET voltage of 1 V, this gives a 10:1
foldback current range.
1,2
M1
Figure 50. 200 W Constant Power Scope Plot, CH1 = VIN; CH2 = VDS;
CH3 = GATE; CH4 = System Current; M1 = FET Power
TIMER
The TIMER pin handles several timing functions with an
external capacitor, CTIMER. There are two comparator thresholds:
VTIMERH (1.0 V) and VTIMERL (0.05 V). The four timing current
sources are a 3 μA pull-up, a 60 μA pull-up, a 2 μA pull-down,
and a 100 μA pull-down.
These current and voltage levels, together with the value of
CTIMER chosen by the user, determine the initial timing cycle
time, the fault current limit time, and the hot swap retry duty
cycle. The TIMER capacitor value is determined using the
following equation:
CTIMER = (tON × 60 μA)/VTIMERH
where tON is the time that the FET is allowed to spend in
regulation. The choice of CTIMER is based on matching this time
with the SOA requirements of the FET. Foldback can be used
here to simplify selection.
When VIN is connected to the backplane supply, the internal
supply of the ADM1075 must be charged up. A very short time
later when the internal supply is fully up and above the undervolt-
age lockout voltage (UVLO), the device comes out of reset.
During this first short reset period, the GATE and TIMER pins
are both held low. The ADM1075 then goes through an initial
Rev. D | Page 23 of 52
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