EVAL-ADM1075EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-ADM1075EBZ
Analog Devices
'EVAL-ADM1075EBZ' PDF : 52 Pages View PDF
ADM1075
PMBus INTERFACE
The I2C bus is a common, simple serial bus used by many devices
to communicate. It defines the electrical specifications, the bus
timing, the physical layer, and some basic protocol rules.
SMBus is based on I2C and aims to provide a more robust and
fault-tolerant bus. Functions such as bus timeout and packet
error checking are added to help achieve this robustness, along
with more specific definitions of the bus messages used to read
and write data to devices on the bus.
PMBus is layered on top of SMBus and, in turn, on I2C. Using the
SMBus defined bus messages, PMBus defines a set of standard
commands that can be used to control a device that is part of a
power chain.
The ADM1075 command set is based upon the PMBus™ Power
System Management Protocol Specification, Part I and Part II,
Revision 1.2. This version of the standard is intended to provide
a common set of commands for communicating with dc-to-dc
type devices. However, many of the standard PMBus commands
can be mapped directly to the functions of a hot swap controller.
Part I and Part II of the PMBus standard describe the basic
commands and how they can be used in a typical PMBus setup.
The following sections describe how the PMBus standard and
the ADM1075 specific commands are used.
DEVICE ADDRESSING
The ADM1075 is available in two models: the ADM1075-1 and
ADM1075-2. The PMBus address is seven bits in size. The
upper five bits (MSBs) of the address word are fixed and are
different for each model, as follows:
• ADM1075-1: Base address is 00100xx (0x10)
• ADM1075-2: Base address is 00110xx (0x18)
The ADM1075-1 and ADM1075-2 have a single ADR pin that
is used to select one of four possible addresses for a given
model. The ADR pin connection selects the lowest two bits
(LSBs) of the 7-bit address word (see Table 6).
Table 6. PMBus Addresses and ADR Pin Connection
Value of Address LSBs
ADR Pin Connection
00
Connect to VEE
01
150 kΩ resistor to VEE
10
No connection (floating)
11
Connect to VCAP
Data Sheet
SMBus PROTOCOL USAGE
All I2C transactions on the ADM1075 are performed using
SMBus defined bus protocols. The following SMBus protocols
are implemented by the ADM1075:
• Send byte
• Receive byte
• Write byte
• Read byte
• Write word
• Read word
• Block read
PACKET ERROR CHECKING
The ADM1075 PMBus interface supports the use of the packet
error checking (PEC) byte that is defined in the SMBus standard.
The PEC byte is transmitted by the ADM1075 during a read
transaction or sent by the bus host to the ADM1075 during a
write transaction. The ADM1075 supports the use of PEC with
all the SMBus protocols that it implements.
The use of the PEC byte is optional. The bus host can decide
whether to use the PEC byte with the ADM1075 on a message-
by-message basis. There is no need to enable or disable PEC in
the ADM1075.
The PEC byte is used by the bus host or the ADM1075 to detect
errors during a bus transaction, depending on whether the trans-
action is a read or a write. If the host determines that the PEC
byte read during a read transaction is incorrect, it can decide to
repeat the read if necessary. If the ADM1075 determines that the
PEC byte sent during a write transaction is incorrect, it ignores
the command (does not execute it) and sets a status flag.
Within a group command, the host can choose to send or not
send a PEC byte as part of the message to the ADM1075.
PARTIAL TRANSACTIONS ON I2C BUS
In the event of a specific sequence of events occurring on the
I2C bus, it is possible for the I2C interface on the device to go
into a state where it fails to ACK the next I2C transaction directed
to it. There are two ways that this behavior can be triggered:
• A partial I2C transaction consisting of a start condition,
followed by a single SCL clock pulse and stop condition.
• If the I2C bus master does not follow the 300 ns SDA data
hold time when signaling the ACK/NACK bit at the end of
a transaction. The device sees this as a single SCL clock
partial transaction.
In the event that the device NACKs a transaction, then the I2C
interface on the device can be reset by sending a series of up to
16 SCL clock pulses, or performing a dummy transaction to
another I2C address on the bus.
Rev. D | Page 28 of 52
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