EVAL-CED1Z View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-CED1Z
Analog Devices
'EVAL-CED1Z' PDF : 32 Pages View PDF
Data Sheet
AD7262
Power-Up Conditions
On power-up, the status of the gain pins determine which mode
of operation is selected, as outlined in the Gain Selection section.
All registers are set to 0 by default.
If the AD7262/AD7262-5 are powered up in pin-driven mode,
the gain pins and the PDx pins should be configured to the
appropriate logic states and a calibration initiated if required.
Alternatively, if the AD7262/AD7262-5 are powered up in control
register mode, the comparators and ADCs are powered down
and the default gain is 1. Thus, powering up in control register
mode requires a write to the device to power up the
comparators and the ADCs.
It takes 15 μs to power up the AD7262/AD7262-5 when using
an external reference. When the internal reference is used, 240 μs
are required to power up the AD7262/AD7262-5 with a 1 μF
decoupling capacitor.
CONTROL REGISTER
The control register on the AD7262/AD7262-5 is a 12-bit read
and write register, which is used to control the device when not
in pin-driven mode. The PD0/DIN pin serves as the serial DIN pin
for the AD7262/AD7262-5 when the gain pins are set to 0 (that
is, the part is not in pin-driven mode). The control register can
be used to select the gain of the PGAs, the power-down modes,
and the calibration of the offset for both ADC A and ADC B.
When operating in the control register mode, PD1 and PD2
should be connected to a low logic state.
These functions can also be implemented by setting the logic
levels on the gain pins, the power-down pins, and the CAL pin,
respectively. The control register can also be used to read the
offset and gain registers.
Data is loaded from the PD0/DIN pin of the AD7262/AD7262-5
on the falling edge of SCLK when CS is in a logic low state. The
control register is selected by first writing the appropriate four
WR bits, as outlined in Table 10. The 12 data bits must then be
clocked into the control register of the device. Thus, on the 16th
falling SCLK edge, the LSB is clocked into the device. One more
SCLK cycle is then required to write to the internal device registers.
In total, 17 SCLK cycles are required to successfully write to the
AD7262/AD7262-5. The data is transferred on the PD0/DIN line
while the conversion result is being processed. The data transferred
on the DIN line corresponds to the AD7262/ AD7262-5
configuration for the next conversion.
Only the information provided on the 12 falling clock edges
after the CS falling edge and the initial four write address bits is
loaded to the control register. The PD0/DIN pin should have a
logic low state for the four bits RD3 to RD0 when using the
control register to select the power-down modes or gain setting
or when initializing a calibration. The RD bits should also be set
to a logic low level to access the ADC results from both DOUTA
and DOUTB.
The power-up status of all bits is 0 and the MSB denotes the first
bit in the data stream. The bit functions are outlined in Table 8
and Table 9.
Table 8. Control Register Bits
MSB
Bit 11 Bit 10 Bit 9
Bit 8
RD3
RD2
RD1
RD0
Bit 7
CAL
Bit 6
PD2
Bit 5
PD1
Bit 4
PD0
Bit 3
G3
Bit 2
G2
Bit 1
G1
LSB
Bit 0
G0
Table 9. Control Register Bit Function Description
Bits
Mnemonic Description
11 to 8
7
RD3 to RD0
CAL
Register address bits. These bits select which register the subsequent read is from. See Table 11.
Setting this bit high initiates an internal offset calibration. Once the calibration is completed, this pin can be reset low,
and the internal offset, which is stored in the on-chip offset registers, is automatically removed from the ADC results.
6 to 4 PD2 toPD0 Power-down bits. These bits select which power-down mode is programmed. See Table 7.
3 to 0 G3 to G0
Gain selection bits. These bits select which gain setting is used on the front-end PGA. See Table 6.
Table 10. Write Address Bits
WR3
WR2
0
0
WR1
0
WR0
1
Read Register Addressed
Control register
CS
SCLK
DOUTA
PD0/DIN
t2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
THREE-STATE
t13
t14
WR3 WR2 WR1 WR0 RD3 RD2 RD1 RD0 CAL PD2 PD1 PD0 G3 G2 G1 G0
DB11 DB10
THREE-STATE
Figure 30. Timing Diagram for a Write Operation to the Control Register
t8
30 31
DB0
tQUIET
THREE-
STATE
Rev. B | Page 23 of 32
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