EVAL-CED1Z3 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-CED1Z3' PDF : 28 Pages View PDF
AD7626
THEORY OF OPERATION
IN+
GND
REF
(4.096V)
GND
IN–
MSB
32,768C 16,384C
32,768C 16,384C
MSB
4C
2C
4C
2C
LSB SW+
SWITCHES
CONTROL
C
C
COMP
CONTROL
LOGIC
CLK+, CLK–
DCO+, DCO–
D+, D–
DATA TRANSFER
C
C
SW–
LSB
OUTPUT CODE
CNV+, CNV–
LVDS INTERFACE
GND
CONVERSION
CONTROL
Figure 27. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7626 is a 10 MSPS, high precision, power effi-
cient, 16-bit ADC that uses SAR-based architecture to
provide a performance of 91.5 dB SNR, ±0.45 LSB INL,
and ±0.35 LSB DNL.
The AD7626 is capable of converting 10,000,000 samples per
second (10 MSPS). The device typically consumes 136 mW of
power. The AD7626 offers the added functionality of a high
performance on-chip reference and on-chip reference buffer.
The AD7626 is specified for use with 5 V and 2.5 V supplies
(VDD1, VDD2). The interface from the digital host to the
AD7626 uses 2.5 V logic only. The AD7626 uses an LVDS
interface to transfer data conversions. The CNV+ and CNV−
inputs to the part activate the conversion of the analog input.
The CNV+ and CNV− pins can be applied using a CMOS or
LVDS source.
The AD7626 is housed in a space-saving, 32-lead, 5 mm ×
5 mm LFCSP.
CONVERTER INFORMATION
The AD7626 is a 10 MSPS ADC that uses SAR-based archi-
tecture to incorporate a charge redistribution DAC. Figure 27
shows a simplified schematic of the ADC. The capacitive DAC
consists of two identical arrays of 16 binary weighted capacitors
that are connected to the two comparator inputs.
During the acquisition phase, the terminals of the array tied
to the input of the comparator are connected to GND via SW+
and SW−. All independent switches are connected to the analog
inputs. In this way, the capacitor arrays are used as sampling
capacitors and acquire the analog signal on the IN+ and IN−
inputs. A conversion phase is initiated when the acquisition
phase is complete and the CNV input goes high. Note that the
AD7626 can receive a CMOS or LVDS format CNV signal.
When the conversion phase begins, SW+ and SW− are opened
first. The two capacitor arrays are then disconnected from the
inputs and connected to the GND input. Therefore, the differential
voltage between the inputs (IN+ and IN−) captured at the end
of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced. By switching
each element of the capacitor array between GND and 4.096 V
(the reference voltage), the comparator input varies by binary
weighted voltage steps (VREF/2, VREF/4 … VREF/65,536). The
control logic toggles these switches, MSB first, to bring the
comparator back into a balanced condition. At the completion
of this process, the control logic generates the ADC output code.
The AD7626 digital interface uses low voltage differential
signaling (LVDS) to enable high data transfer rates.
The AD7626 conversion result is available for reading after
tMSB (time from the conversion start until MSB is available) has
elapsed. The user must apply a burst LVDS CLK± signal to the
AD7626 to transfer data to the digital host.
The CLK± signal outputs the ADC conversion result onto the
data output D±. The bursting of the CLK± signal is illustrated
in Figure 41 and Figure 42 and is characterized as follows:
• The differential voltage on CLK± should be held steady
state in the time between tCLKL and tMSB.
• The AD7626 has two data read modes. For more
information about the echoed-clock and self-clocked
interface modes, see the Digital Interface section.
Rev. A | Page 15 of
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