EVAL-SDP-CH1Z View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-SDP-CH1Z' PDF : 28 Pages View PDF
AD7626
DIGITAL INTERFACE
Conversion Control
All analog-to-digital conversions are controlled by the CNV±
signal. This signal can be applied in the form of a CNV+/CNV−
LVDS signal, or it can be applied in the form of a 2.5 V CMOS
logic signal to the CNV+ pin. The conversion is initiated by the
rising edge of the CNV± signal.
After the AD7626 is powered up, the first conversion result
generated is invalid. Subsequent conversion results are valid
provided that the time between conversions does not exceed
the maximum specification for tCYC.
The two methods for acquiring the digital data output of the
AD7626 via the LVDS interface are described in the following
sections.
Echoed-Clock Interface Mode
The digital operation of the AD7626 in echoed-clock interface
mode is shown in Figure 41. This interface mode, requiring
only a shift register on the digital host, can be used with many
digital hosts (such as FPGA, shift register, and microprocessor).
It requires three LVDS pairs (D±, CLK±, and DCO±) between
each AD7626 and the digital host.
CNV–
CNV+
SAMPLE N
tCNVH
tCYC
The clock DCO± is a buffered copy of CLK± and is synchronous
to the data, D±, which is updated on the falling edge of DCO +
(tD). By maintaining good propagation delay matching between
D± and DCO± through the board and the digital host, DCO
can be used to latch D± with good timing margin for the shift
register.
Conversions are initiated by a rising edge CNV± pulse. The
CNV± pulse must be returned low (≤ tCNVH maximum) for
valid operation. After a conversion begins, it continues until
completion. Additional CNV± pulses are ignored during the
conversion phase. After the time, tMSB, elapses, the host should
begin to burst the CLK±. Note that, tMSB, is the maximum time
for the MSB of the new conversion result and should be used as
the gating device for CLK±. The echoed clock, DCO±, and the
data, D, are driven in phase with D± being updated on the
falling edge of DCO+; the host should use the rising edge of
DCO+ to capture D±. The only requirement is that the 16
CLK± pulses finish before the time (tCLKL) elapses of the next
conversion phase or the data is lost. From the tCLKL to tMSB, D±
and DCO± are driven to 0. Set CLK± to idle low between CLK±
bursts.
SAMPLE N + 1
ACQUISITION
tCLK
CLK–
CLK+
DCO–
tDCO
DCO+
D+
tCLKD
D–
15 16
ACQUISITION
1
2
tCLKL
15 16
15 16
1
2
15 16
tMSB
D1 D0
N–1 N–1
0
tD
D15
D14
N
N
D1 D0
N
N
0
Figure 41. Echoed-Clock Interface Mode Timing Diagram
ACQUISITION
1
2
3
1
2
3
D15
N+1
D14 D13
N+1 N+1
Rev. A | Page 22 of 2
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