EVAL-SDP-CH1Z View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-SDP-CH1Z' PDF : 28 Pages View PDF
AD7626
APPLICATIONS INFORMATION
LAYOUT, DECOUPLING, AND GROUNDING
When laying out the printed circuit board (PCB) for the AD7626,
follow the practices described in this section to obtain the maxi-
mum performance from the converter.
Exposed Paddle
The AD7626 has an exposed paddle on the underside of the
package.
• Solder the paddle directly to the PCB.
• Connect the paddle to the ground plane of the board using
multiple vias, as shown in Figure 43.
• Decouple all supply pins except for Pin 12 (VIO) directly to
the paddle, minimizing the current return path.
• Pin 13 and Pin 24 can be connected directly to the paddle.
Use vias to ground at the point where these pins connect to
the paddle.
VDD1 Supply Routing and Decoupling
The VDD1 supply is connected to Pin 1, Pin 19, and Pin 20.
Decouple the supply using a 100 nF capacitor at Pin 1. The user
can connect this supply trace to Pin 19 and Pin 20. Use a series
ferrite bead to connect the VDD1 supply from Pin 1 to Pin 19
and Pin 20. The ferrite bead isolates any high frequency noise or
ringing on the VDD1 supply. Decouple the VDD1 supply to Pin
19 and Pin 20 using a 100 nF capacitor decoupled to ground at
the exposed paddle.
VIO Supply Decoupling
Decouple the VIO supply applied to Pin 12 to ground at Pin 13.
Layout and Decoupling of Pin 25 to Pin 32
Connect the outputs of Pin 25, Pin 26, and Pin 28 together and
decouple them to Pin 27 using a 10 μF capacitor with low ESR
and low ESL.
Reduce the inductance of the path connecting Pin 25, Pin 26,
and Pin 28 by widening the PCB traces connecting these pins.
Take a similar approach in the connections used for the
reference pins of the AD7626. Connect Pin 29, Pin 30, and
Pin 32 together using widened PCB traces to reduce inductance.
In internal or external reference mode, a 4.096 V reference voltage
is output on Pin 29, Pin 30, and Pin 32. Decouple these pins to
Pin 31 using a 10 μF capacitor with low ESR and low ESL.
Figure 43 shows an example of the recommended layout for
the underside of the AD7626 device. Note the extended signal
trace connections and the outline of the capacitors decoupling
the signals applied to the REF pins (Pin 29, Pin 30, and Pin 32)
and to the CAP2 pins (Pin 25, Pin 26, and Pin 28).
4.096V
EXTERNAL REFERENCE
(ADR434 OR ADR444)
24 23 22 21 20 19 18 17
25
16
26
PADDLE
15
27
14
28
13
29
12
30
11
31
10
32
9
12345678
Figure 43. PCB Layout and Decoupling Recommendations for Pin 24 to Pin 32
Rev. A | Page 24 of 2
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