EVAL1002/AA View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'EVAL1002/AA' PDF : 20 Pages View PDF
TSA1002
Data Ready (DR)
The Data Ready output is an image of the clock
being synchronized on the output data (D0 to D9).
This is a very helpful signal that simplifies the
synchronization of the measurement equipment or
the controlling DSP.
As digital output, DR goes in high impedance state
when OEB is asserted to High level as described
in the timing diagram page 4.
REFERENCES AND COMMON MODE
CONNECTION
VREFM must be always connected externally.
The VREFP, VREFM voltages set the analog
N dynamic at the input of the converter that has a full
scale amplitude of 2*(VREFP-VREFM).
In case of analog dynamic lower than 2Vpp, the
best linearity and distortion performance is
G achieved while increasing the VREFM voltage
I instead of lowering the VREFP one.
The INCM is the mid voltage of the analog input
S signal.
E It is possible to use an external reference voltage
D device for specific applications requiring even
better linearity, accuracy or enhanced
temperature behavior.
Internal reference and common mode
W In the default configuration, the ADC operates with
its own reference and common mode voltages
E t(s) generated by its internal bandgap. VREFM pin is
connected externally to the Analog Ground while
N c VREFP (respectively INCM) is set to its internal
u voltage of 1.03V (respectively 0.57V). It is
d recommended to decouple the VREFP in order to
R ro minimize low and high frequency noise (refer to
P Figure 1)
O te Figure 1 : Internal reference and common mode
le setting
F bso 1.03V
330pF 10nF 4.7uF
T O VIN VREFP
- TSA1002
O t(s) VINB
INCM
VREFM
0.57V
330pF 10nF
4.7uF
N Produc External reference and common mode
te Each of the voltages VREFM, VREFP and INCM
le can be fixed externally to better fit to the
o application needs (Refer to Table íOPERATING
Obs CONDITIONSí p2 for min and max values).
Using the STMicroelectronics TS821 or
TS4041-1.2 Vref leads to optimum performances
when configured as shown on Figure 2.
Figure 2 : External reference setting
1kΩ
VCCA VREFP
VIN
TSA1002
VINB
VREFM
330pF 10nF 4.7uF
TS821
TS4041
external
reference
At 15Msps sampling frequency, 1MHz input
frequency and -1dBFS amplitude signal,
performances can be improved up to 2dB on
SFDR and 0.3dB on SINAD. At 50Msps sampling
frequency, 1MHz input frequency and -1dBFS
amplitude signal, performances can be improved
up to 1dBc on SFDR and 0.6dB on SINAD.
This can be very helpful for example for
multichannel application to keep a good matching
among the sampling frequency range.
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