EVAL1002/AA View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'EVAL1002/AA' PDF : 20 Pages View PDF
TSA1002
Power consumption
Distortion vs. Duty cycle
The internal architecture of the TSA1002 enables
to optimize the power consumption according to
the sampling frequency of the application. For this
purpose, a resistor is placed between IPOL and
the analog Ground pins. The figure 10 sums up
the relevant data.
N Fs=50MSPS; consumption optimized; Fin=1MHz
-30
-40
-50
I G 70
60
The TSA1002 will combine highest performances
and lowest consumption at 50Msps when Rpol is
in the range of 12kΩ to 20kΩ.
At lower sampling frequency, this value of resistor
may be changed and the consumption will
decrease as well.
-60
-70
STHD
-80
-90
E
SFDR
-100
-110
D
IccA
50
40
30
20
Figure 10 : Analog Current consumption vs. Fs
-120
10
According value of Rpol polarization resistance
W 60
E ) 50
t(s 40
N c 30
du 20
R ro 10
O te P 0
le 25
RPOL
ICCA
35
45
55
65
Fs (MHz)
20
18
16
14
12
10
8
6
4
2
0
75
F bso Linearity, distortion performance towards
T O Clock Duty Cycle variation
) - The TSA1002 has an outstanding behaviour
O t(s towards clock duty cycle variation and it may be
c also reinforced with adjustment of analog current
N u consumption.
rod Linearity vs. Duty cycle
Fs=50MSPS; consumption optimized; Fin=1MHz
te P 80
10
le ENOB
70
9
so60
SNR
8
b 50
SINAD
O7
30
40
50
60
70
Duty Cycle (%)
Linearity vs. Duty cycle
Fs=50MSPS; Icca=20mA; Fin=10MHz
80
75
70
65
60
55
50
45
40
35
30
40
ENOB
SNR
SINAD
45
50
55
Duty Cycle (%)
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
60
Distortion vs. Duty cycle
Fs=50MSPS; Icca=20mA; Fin=10MHz
0
-10
-20
-30
-40
-50
40
THD
IccA
6
-60
30
20
-70
5
-80
SFDR
10
4
-90
0
3
30
40
50
60
70
Duty Cycle (%)
-100
40
45
50
55
60
Duty Cycle (%)
16/20
Share Link: 
