2.3.2.Read/Write Operation Sequence (VRAM)
READ
Parameter
AB[15:0] and MEMCS valid before MEMRD↓
AB[15:0] and MEMCS hold from MEMRD ↑
MEMRD↓ to READY↓
READY↑ to DB[7:0] valid
DB[7:0] hold from MEMRD↑
MEMRD↑ to DB[7:0] Hi-z delay
READY negated pluse width
Symbol
t1
t2
t3
t4
t5
t6
t7
AB[15:0]
VALID
VCC1=4.5~5.5V
Min.
Max.
Units
0
-
ns
0
-
ns
-
20
ns
-
10
ns
-
10
ns
-
20
ns
- 3.5×MCLK+10 ns
MEMCS
t1
t2
MEMRD
t3
t7
READY
Hi-z
Hi-z
t4
t6
t5
Hi-z
Hi-z
DB[7:0]
VALID
Where MCLK=1/fosc or 2/fosc depending on which display mode the chip is in ( See Section 2.3.3 )
WRITE
Parameter
AB[15:0] and MEMCS valid before MEMWR↓
AB[15:0] and MEMCS hold from MEMWR↑
MEMWR↓ to READY↓
MEMWR↓ to DB[7:0] valid
DB[7:0] hold from MEMWR↑
READY negated pluse width
Symbol
t1
t2
t3
t4
t5
t6
VCC1=4.5~5.5V
Min.
Max.
Units
0
-
ns
0
-
ns
-
20
ns
-
MCLK-20
ns
0
-
ns
- 3.5×MCLK+10 ns
AB[15:0]
VALID
t1
MEMCS
t2
MEMW R
t3
Hi-Z
READY
t6
Hi-Z
DB[7:0]
t4
Hi-Z
t5
Hi-Z
VALID
Where MCLK=1/fosc or 2/fosc depending on which display mode the chip is in ( See Section 2.3.3 )
F-51136NCWHU-FW-AA (AA) No.2000-0230
OPTREX CORPORATION
OPTREX
Page 6/19