FDC37C666GT View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

FDC37C666GT

High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers

SMSC -> Microchip 

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DATA RATE SELECT REGISTER (DSR)

Address 3F4 WRITE ONLY

This register is write only. It is used to program

the data rate, amount of write precompensation,

power down status, and software reset. The

data rate is programmed using the

Configuration Control Register (CCR) not the

DSR, for PC/AT and PS/2 Model 30 and

Microchannel applications. Other applications

can set the data rate in the DSR. The data rate

of the floppy controller is the most recent write

of either the DSR or CCR. The DSR is

unaffected by a software reset. A hardware

reset will set the DSR to 02H, which

corresponds to the default precompensation

setting and 250kb/s.

7

6

5

4

3

2

1

0

S/W POWER 0

PRE- PRE- PRE- DRATE DRATE

RESET DOWN

COMP2 COMP1 COMP0 SEL1 SEL0

RESET 0

0

0

0

0

0

1

0

COND.

BIT 0 and 1 DATA RATE SELECT

These bits control the data rate of the floppy

controller. See Table 13 for the settings

corresponding to the individual data rates. The

data rate select bits are unaffected by a

software reset, and are set to 250kb/s after a

hardware reset.

BIT 2 through 4 PRECOMPENSATION

SELECT

These three bits select the value of write

precompensation that will be applied to the

WDATA output signal. Table 12 shows the

precompensation values for the combination of

these bits settings. Track 0 is the default

starting track number to start precompensation.

this starting track number can be changed by

the configure command.

BIT 5 UNDEFINED

Should be written as a logic "0".

BIT 6 LOW POWER

A logic "1" written to this bit will put the floppy

controller into Manual Low Power mode. The

floppy controller clock and data separator

circuits will be turned off. The controller will

come out of manual low power mode after a

software reset or access to the Data Register or

Main Status Register.

BIT 7 SOFTWARE RESET

This active high bit has the same function as the

DOR RESET (DOR bit 2) except that this bit is

self clearing.

Table 12 - Precompensation Delays

PRECOMP

432

PRECOMPENSATION

DELAY

111

0.00 ns-DISABLED

001

41.67 ns

010

83.34 ns

011

125.00 ns

100

166.67 ns

101

208.33 ns

110

250.00 ns

000

Default (See Table 14)

33

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