FDC37C666GT View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
FDC37C666GT
SMSC -> Microchip
'FDC37C666GT' PDF : 152 Pages View PDF
Table 13 - Data Rates
DRATESEL
DATA RATE
1
0
MFM
FM
1
1
1 Mbps
Illegal
0
0 500 Kbps 250 Kbps
0
1 300 Kbps 150 Kbps
1
0 250 Kbps 125 Kbps
Table 14 - Default Precompensation Delays
DATA RATE
PRECOMPENSATION
DELAYS
1 Mbps
500 Kbps
300 Kbps
250 Kbps
41.67 ns
125 ns
125 ns
125 ns
MAIN STATUS REGISTER
Address 3F4 READ ONLY
The Main Status Register is a read-only register
and indicates the status of the disk controller.
The Main Status Register can be read at any
time. The MSR indicates when the disk
controller is ready to receive data via the Data
Register. It should be read before each byte
transferring to or from the data register except in
DMA mode. NO delay is required when reading
the MSR after a data transfer.
7
6
5
4
3
2
1
0
RQM
DIO
NON CMD DRV3 DRV2 DRV1 DRV0
DMA BUSY BUSY BUSY BUSY BUSY
BIT 0 - 3 DRV x BUSY
These bits are set to 1s when a drive is in the
seek portion of a command, including implied
and overlapped seeks and recalibrates.
BIT 4 COMMAND BUSY
This bit is set to a 1 when a command is in
progress. This bit will go active after the
command byte has been accepted and goes
inactive at the end of the results phase. If there
is no result phase (Seek, Recalibrate
commands), this bit is returned to a 0 after the
last command byte.
BIT 5 NON-DMA
This mode is selected in the SPECIFY
command and will be set to a 1 during the
execution phase of a command. This is for
polled data transfers and helps differentiate
between the data transfer phase and the reading
of result bytes.
BIT 6 DIO
Indicates the direction of a data transfer once a
RQM is set. A 1 indicates a read and a 0
indicates a write is required.
BIT 7 RQM
Indicates that the host can transfer data if set to
a 1. No access is permitted if set to a 0.
34
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