FDMF6840C View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
MFG CO.
'FDMF6840C' PDF : 19 Pages View PDF
Adaptive Gate Drive Circuit
The driver IC advanced design ensures minimum
MOSFET dead-time, while eliminating potential shoot-
through (cross-conduction) currents. It senses the state
of the MOSFETs and adjusts the gate drive adaptively
to ensure they do not conduct simultaneously. Figure 27
provides the relevant timing waveforms. To prevent
overlap during the LOW-to-HIGH switching transition
(Q2 off to Q1 on), the adaptive circuitry monitors the
voltage at the GL pin. When the PWM signal goes
HIGH, Q2 begins to turn off after a propagation delay
(tPD_PHGLL). Once the GL pin is discharged below 1.0 V,
Q1 begins to turn on after adaptive delay tD_DEADON.
To preclude overlap during the HIGH-to-LOW transition
(Q1 off to Q2 on), the adaptive circuitry monitors the
voltage at the GH-to-PHASE pin pair. When the PWM
signal goes LOW, Q1 begins to turn off after a
propagation delay (tPD_PLGHL). Once the voltage across
GH-to-PHASE falls below 2.2 V, Q2 begins to turn on
after adaptive delay tD_DEADOFF.
V IH_PWM
PWM
GH
to
VSWH
V IL_PWM
t D_HOLD-OFF
V IH_PWM
t R_GH
V TRI_HI
V IH_PWM
tF_GH
V IH_PWM
V TRI_HI
V TRI_LO
V IL_PWM
9 0%
1 0%
CCM
VSWH
GL
90%
1.0V
2.2V
t R_GL
1 0%
t PD_PHGLL
t PD_PLGHL
t D_DEADON
tD_DEADOFF
DCM
t F_GL
DCM
Enter
3-state
t t PD_TSGHH
D_HOLD-OFF
Exit
3 - state
Enter
3 - state
t PD_TSGHH
Exit
3 - state
V IN
V OUT
9 0%
1 0%
t t D_HOLD-OFF PD_TSGLH
Enter
3 - state
Exit
3 - state
Notes:
tPD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal.
Example (tPD_PHGLL – PWM going HIGH to LS VGS (GL) going LOW)
tD_xxx = delay from IC generated signal to IC generated signal. Example (tD_DEADON – LS VGS (GL) LOW to HS VGS (GH) HIGH)
PWM
tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS
tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS
tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (SMOD# held LOW)
Exiting 3-state
tPD_TSGHH = PWM 3-state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS
tPD_TSGLH = PWM 3-state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS
SMOD#
tPD_SLGLL = SMOD# fall to LS VGS fall, VIL_SMOD to 90% LS VGS
tPD_SHGLH = SMOD# rise to LS VGS rise, VIH_SMOD to 10% LS VGS
Dead Times
tD_DEADON = LS VGS fall to HS VGS rise, LS-comp trip value (~1.0V GL) to 10% HS VGS
tD_DEADOFF = VSWH fall to LS VGS rise, SW-comp trip value (~2.2V VSWH) to 10% LS VGS
Figure 27. PWM and 3-StateTiming Diagram
© 2015 Fairchild Semiconductor Corporation
FDMF6840C • Rev. 1.0
13
www.fairchildsemi.com
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