FDMF6840C View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
MFG CO.
'FDMF6840C' PDF : 19 Pages View PDF
Application Information
Supply Capacitor Selection
For the supply inputs (VCIN), a local ceramic bypass
capacitor is recommended to reduce noise and to
supply the peak current. Use at least a 1 µF X7R or X5R
capacitor. Keep this capacitor close to the VCIN pin and
connect it to the GND plane with vias.
Bootstrap Circuit
VCIN Filter
The VDRV pin provides power to the gate drive of the
high-side and low-side power MOSFET. In most cases,
it can be connected directly to VCIN, the pin that
provides power to the logic section of the driver. For
additional noise immunity, an RC filter can be inserted
between the VDRV and VCIN pins. Recommended
values would be 10 Ω and 1 µF.
The bootstrap circuit uses a charge storage capacitor Power Loss and Efficiency
(CBOOT), as shown in Figure 30. A bootstrap capacitance
of 100 nF X7R or X5R capacitor is usually adequate. A
series bootstrap resistor may be needed for specific
Measurement and Calculation
Refer to Figure 30 for power loss testing method.
applications to improve switching noise immunity. The Power loss calculations are:
boot resistor may be required when operating above
15 VIN and is effective at controlling the high-side
PIN=(VIN x IIN) + (V5V x I5V) (W)
(1)
MOSFET turn-on slew rate and VSHW overshoot. RBOOT PSW=VSW x IOUT (W)
(2)
values from 0.5 to 3.0 Ω are typically effective in POUT=VOUT x IOUT (W)
(3)
reducing VSWH overshoot.
PLOSS_MODULE=PIN - PSW (W)
(4)
PLOSS_BOARD=PIN - POUT (W)
(5)
EFFMODULE=100 x PSW/PIN (%)
(6)
EFFBOARD=100 x POUT/PIN (%)
(7)
V 5V
A
I 5V
C VDRV
RVCIN
CVCIN
A
VIN
IIN
C VIN
DISB#
PWM
Input
OFF
ON
Open -
Drain
Output
DISB#
VDRV
VCIN
PWM
FFDDMF6678450C
F0
SMOD#
THW N#
CGND
PGND
VIN
BOOT
VSWH
R BOOT
C BOOT
PHASE
L OUT
V VSW
C OUT
I OUT
A
VOUT
V 5V
DISB#
PWM
Input
OFF
ON
Open-
Drain
Output
Figure 29. Block Diagram With VCIN Filter
A
I 5V
CVDRV
A
VIN
IIN
CVIN
VDRV
VCIN
VIN
DISB#
PWM FFDDMMF68450C
F
SMOD#
THW N#
CGND
PGND
BOOT
VSWH
RBOOT
CBOOT
PHASE
L OUT
V VSW
COUT
IOUT
A
© 2015 Fairchild Semiconductor Corporation
FDMF6840C • Rev. 1.0
Figure 30. Power Loss Measurement
15
www.fairchildsemi.com
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