GL602USB View Datasheet(PDF) - Genesys Logic
Part Name
Description
MFG CO.
'GL602USB' PDF : 35 Pages View PDF
1.0
0.8
0.6
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0.2
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
Common Mode Input Voltage (volts)
Figure 4-3 Differential Input Sensitivity over Entire Common Mode Range
The data receivers for all types of devices must be able to properly decode the differential data in the presence of
jitter. The more of the bit time that any data edge can occupy and still be decoded, the more reliable the data
transfer will be. Data receivers are required to decode differential data transitions that occur in a window plus and
minus a nominal quarter bit time from the nominal (centered) data edge position. Jitter will be caused by the delay
mismatches and by mismatches in the source and destination data rates (frequencies).
TPERIOD
Differential
Data Lines
TJR
TJR1
TJR2
Consecutive
Transitions
N * TPERIOD + TJR1
Paired
Transitions
N * TPERIOD + TJR2
Figure 4-4 Receiver Jitter Tolerance
The source of data can have some variation (jitter) in the timing of edges of the data transmitted. The time between
any set of data transitions is N*TPeriod ± jitter time, where N is the number of bits between the transitions and TPeriod
is defined as the actual period of the data rate. The data jitter is measured with the same capacitive load used for
maximum rise and fall times and is measured at the crossover points of the data lines.
For low-speed transmissions, the jitter time for any consecutive differential data transitions must be within ±25ns
and within ±10ns for any set of paired differential data transitions. These jitter numbers include timing variations
due to differential buffer delay, rise/fall time mismatches, internal clock source jitter, noise and other random
effects.
The output rise time and fall time are measured between 10% and 90% of the signal. Edge transition time for the
rising and falling edges of low-speed signals is 75ns (minimum) into a capacitive load (CL) of 50pF and 300ns
(maximum) into a capacitive load of 350pF. The rising and falling edges should be transitioning (monotonic)
smoothly when driving the cable to avoid excessive EMI.
Revision 1.6
-20-
02/28/2000
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