GL603USB View Datasheet(PDF) - Genesys Logic
Part Name
Description
MFG CO.
'GL603USB' PDF : 41 Pages View PDF
GL603USB/GL603USB-A/GL603USB-B
TPERIOD
Differential
Data Lines
TJ R
TJR1
TJR2
Consecutive
Transitions
N * TPERIOD + TJR1
Paired
Transitions
N * TPERIOD + TJR2
Figure 4-4 Receiver Jitter Tolerance
The source of data can have some variation (jitter) in the timing of edges of the data transmitted. The time
between any set of data transitions is N*TPeriod ± jitter time, where N is the number of bits between the
transitions and TPeriod is defined as the actual period of the data rate. The data jitter is measured with the
same capacitive load used for maximum rise and fall times and is measured at the crossover points of the
data lines.
For low-speed transmissions, the jitter time for any consecutive differential data transitions must be within
±25ns and within ±10ns for any set of paired differential data transitions. These jitter numbers include
timing variations due to differential buffer delay, rise/fall time mismatches, internal clock source jitter,
noise and other random effects.
The output rise time and fall time are measured between 10% and 90% of the signal. Edge transition time
for the rising and falling edges of low-speed signals is 75ns (minimum) into a capacitive load (CL) of 50pF
and 300ns (maximum) into a capacitive load of 350pF. The rising and falling edges should be transitioning
(monotonic) smoothly when driving the cable to avoid excessive EMI.
Rise Time
CL
Differential
Data Lines
10%
90%
CL
tR
Fall Time
90%
10%
tF
Full Speed: 4 to 20ns at CL = 50pF
Low Speed: 75ns at CL = 50pF, 300ns at CL = 350pF
Figure 4-5 Data Signal Rise and Fall Time
4.8.3 Serial Interface Engine (SIE)
The SIE manages data movement between the CPU and the transceiver. The SIE handles both transmit and
receive operations on the USB. It contains the logic used to manipulate the transceiver and the endpoint
registers.
24
09/22/00
Revision 1.4
Share Link: 
