GL830 View Datasheet(PDF) - Genesys Logic
Part Name
Description
MFG CO.
'GL830' PDF : 29 Pages View PDF
GL830 USB2.0 to SATA Bridge Controller
V5
52
p 5V Power Input
Pin Name
DD0~15
ARESET_
CS1_, CS0_
DA0~2
INTRQ
DMACK_
IORDY
DIOR_
DIOW_
DMARQ
ATA/ ATAPI Interface (Host mode)
Pin# Type
Description
44,40,36,
30,26,14,
10,6,8,12, B IDE Data Bus
21,28,32,
38,42,46
127
I
(pu)
Device Reset
85, 83
I
Chip Select #1,#0
(pu)
79,78,81
I
(pd)
IDE Address #2,#1,#0
65
O IDE interrupt input
62
I
(pu)
IDE Acknowledge
60
O IDE Ready
58
I
(pu)
IDE read signal
56
I
(pu)
IDE write signal
54
O IDE request
Pin Name
DD0~15
ARESET_
CS1_, CS0_
DA0~2
INTRQ
DMACK_
IORDY
DIOR_
DIOW_
DMARQ
ATA/ ATAPI Interface (Device mode)
Pin# Type
Description
44,40,36,
30,26,14,
10,6,8,12, B IDE Data Bus
21,28,32,
38,42,46
127
O Device Reset
85, 83 O Chip Select #1,#0
79,78,81
65
62
60
58
O IDE Address #2,#1,#0
I
(pd)
IDE interrupt input
O IDE Acknowledge
I
(pu)
IDE Ready
O IDE read signal
56
O IDE write signal
54
I
(pd)
IDE request
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