GL830 View Datasheet(PDF) - Genesys Logic
Part Name
Description
MFG CO.
'GL830' PDF : 29 Pages View PDF
GL830 USB2.0 to SATA Bridge Controller
Miscellaneous Interface
Pin Name
Pin# Type
Description
TEST
23 I (pd) Test Mode Input
X2
92
B Crystal Output
X1
93
I Crystal Input
HRST_
MODE0,1
GPIO0~4
PIO0~4
TXD
RXD
SPDSEL
PHYRDY
9
I (pu) Reset Pin
19,49
1,61,55,2,
64
33,34,57,
4,3
24
25
128
Mode Select
I
(pd)
00=> USB to SATA; 10=> eSATA to SATA;
01=> USB to PATA; 11=> SATA to PATA
When MODE0,1=11, PIO1=0 is device mode.
When MODE0,1=11, PIO1=1 is host mode.
B
(pu)
General Purpose I/O #0~#4
B Programmable I/O #0~#4
(pd)
O
(pu)
8051 UART TXD
B
(pu)
8051 UART RXD
I 0 => force in 1.5G; 1 => negotiate interface speed with attached
(pd) device (1.5G or 3G)
63
O SATA PHY ready
T_ROM
ROM_A0~14
ROM_D0~7
NC
59
35,31,27,
15,11,5,
125,123,
122,124,
126,7,13,
22,29
37,41,45,
82,84,53,
43,39
80,97,98,
99,100,
101,102,
103
I (pd) 0 => Internal ROM; 1 => External ROM
O ROM Address #0~#14
B
(pd)
ROM Data #0~#7
- No connection
Notation:
Type O
I
B
B/I
B/O
P
A
Output
Input
Bi-directional
Bi-directional, default input
Bi-directional, default output
Power / Ground
Analog
©2007 Genesys Logic Inc. - All rights reserved.
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