GL850A-MNNXX View Datasheet(PDF) - Genesys Logic
Part Name
Description
MFG CO.
'GL850A-MNNXX' PDF : 29 Pages View PDF
GL850A USB 2.0 Low-Power HUB Controller
output mode, and then output high for normal mode.
When GL850A is suspended, this pin will output low.
*For detailed explanation, please see Chapter 5
Gang
input:1, output: 0@normal, 1@suspend
Individual input:0, output: 1@normal, 0@suspend
Clock and Reset Interface
Pin Name
GL850A
I/O Type
48Pin# 64Pin#
Description
X1
14
20
I 12MHz crystal clock input.
X2
15
21
RESET# 28
38
O 12MHz crystal clock output.
Active low. External reset input, default pull high 10KΩ.
I When RESET# = low, whole chip is reset to the initial
state.
System Interface
Pin Name
GL850A
I/O Type
48Pin# 64 Pin#
Description
TEST
29
39
I
0: Normal operation.
(pd) 1: Chip will be put in test mode.
Power / Ground
GL850A
Pin Name
I/O Type
48Pin# 64 Pin#
Description
AVDD
1,7,12, 11,18,22,
16,20 28,64
P 3.3V analog power input for analog circuits.
AGND
2,8,13, 1,12,19,
17,21 23,29
P Analog ground input for analog circuits.
DVDD
DGND
NC
27,34,
39,44
26,33,
38,
43,47
30
37,47,
52,59
36,46,
51,58,62
2,5~7,
10,13,16,
24,27,30,
33
P 3.3V digital power input for digital circuits
P Digital ground input for digital circuits.
- No connection
Note: Analog circuits are quite sensitive to power and ground noise. PCB layout must take care the power
routing and the ground plane. For detailed information, please refer to GL850A Design Guideline.
Notation:
Type O
I
B
B/I
B/O
P
Output
Input
Bi-directional
Bi-directional, default input
Bi-directional, default output
Power / Ground
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 13
Share Link: 
