GLT7256L08-10J3 View Datasheet(PDF) - G-Link Technology
Part Name
Description
MFG CO.
'GLT7256L08-10J3' PDF : 10 Pages View PDF
G-LINK
GLT7256L08
Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM
Mar 2000(REV. 2.0)
Switching Waveform (Write Cycle)
WRITE CYCLE 2(1,6)
Note:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap CE low and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive. The
data input setup and hold timing should be referenced to the second transition edge of the
signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, I/O pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, outputs remain in a high impedance state.
6. OE is continuously low ( OE =VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, I/O pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured ±200mV from steady state with CL=5pF.
11. tCW is measured from CE going low to the end of write.
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
-7-
G-Link Technology Corporation,Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
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