HCMP9650 View Datasheet(PDF) - Signal Processing Technologies
Part Name
Description
MFG CO.
'HCMP9650' PDF : 8 Pages View PDF
TIMING INFORMATION
The timing diagram for the comparator is shown in figure 1.
The latch enable (LE) pulse is shown at the top. If LE is high
in the HCMP96850, the comparator tracks the input differ-
ence voltage. When LE is driven low, the comparator out-
puts are latched into their existing logic states.
The leading edge of the input signal (which consists of a
10 mV overdrive voltage) changes the comparator output
after a time of tpdL or tpdH (Q or Q ). The input signal must be
maintained for a time ts (set-up time) before the latch enable
falling edge and held for time tH after the falling edge for the
comparator to accept data. After tH, the output ignores the
input status until the latch is strobed again. A minimum latch
pulse width of tpL is needed for strobe operation, and the
output transitions occur after a time of tpLOH or tpLOL.
Figure 1 - Timing Diagram
LATCH ENABLE
DIFFERENTIAL
INPUT VOLTAGE
OUTPUT Q
tH
tS
VOD
tpdL
tpL
tpLOH
50%
VREF ± VOS
50%
OUTPUT Q
tpdH
VIN+=100 mV (P-P), VOD =10 mV
tpLOL
50%
The set-up and hold times are a measure of the time required for an input signal to propagate through the first
stage of the comparator to reach the latching circuitry. Input signal changes occurring before tS will be detected
and held; those occurring after tH will not be detected. Changes between tS and tH may or may not be detected.
SWITCHING TERMS (Refer to figure 1)
tpdH
INPUT TO OUTPUT HIGH DELAY - The propagation
delay measured from the time the input signal crosses
the input reference voltage (± the input offset voltage)
to the 50% point of an output LOW to HIGH transition.
tpdL
INPUT TO OUTPUT LOW DELAY - The propagation
delay measured from the time the input signal crosses
the input reference voltage (± the input offset voltage)
to the 50% point of an output HIGH to LOW transition.
tpLOH
LATCH ENABLE TO OUTPUT HIGH DELAY - The
propagation delay measured from the 50% point of the
Latch Enable signal LOW to HIGH transition to 50%
point of an output LOW to HIGH transition.
VOD
VOLTAGE OVERDRIVE - The difference between the
differential input and reference input voltages.
tpLOL
tH
tpL
tS
LATCH ENABLE TO OUTPUT LOW DELAY - The
propagation delay measured from the 50% point of the
Latch Enable signal LOW to HIGH transition to the 50%
point of an output HIGH to LOW transition.
MINIMUM HOLD TIME - The minimum time after the
negative transition of the Latch Enable signal that the
input signal must remain unchanged in order to be
acquired and held at the outputs.
MINIMUM LATCH ENABLE PULSE WIDTH - The
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change.
MINIMUM SET-UP TIME - The minimum time before
the negative transition of the Latch Enable signal that
an input signal change must be present in order to be
acquired and held at the outputs.
SPT
HCMP96850
4
3/18/97
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