HI-3200PCTF View Datasheet(PDF) - Holt Integrated Circuits
Part Name
Description
MFG CO.
'HI-3200PCTF' PDF : 59 Pages View PDF
HI-3200, HI-3201
CAN Bus Received Data Status Byte Definition
CAN RECEIVED DATA BLOCK STATUS BYTE
XX
76
MSB
NEWHNOESWTCNAENWTNXE3WTNXE2WTX1
543210
LSB
Bit Name
R/W Default Description
7-
R/W 0 Not used
6-
R/W 0 Not used
5 NEWHOST R/W 0 This bit is set when a new CAN frame is received and stored in this block. It is reset when
the host CPU executes SPI instruction 0x9C to read the block.
4 NEWCAN
R/W 0 This bit is set when a new CAN frame is received and stored in this block. It is reset when
the CAN Transmit scheduler reads any bytes from the block.
3 NEWTX3
R/W 0 This bit is set when a new CAN frame is received and stored in this block. It is reset when
the ARINC 429 Transmit scheduler #3 reads any bytes from the block.
2 NEWTX2
R/W 0 This bit is set when a new CAN frame is received and stored in this block. It is reset when
the ARINC 429 Transmit scheduler #2 reads any bytes from the block.
1 NEWTX1
R/W 0 This bit is set when a new CAN frame is received and stored in this block. It is reset when
the ARINC 429 Transmit scheduler #1 reads any bytes from the block.
0 NEWTX0
R/W 0 This bit is set when a new CAN frame is received and stored in this block. It is reset when
the ARINC 429 Transmit scheduler #0 reads any bytes from the block.
HOLT INTEGRATED CIRCUITS
25
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