HSDL-7002 View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
'HSDL-7002' PDF : 11 Pages View PDF
Recommended Operating Conditions
(Vcc = 2.7 to 5.5 V, TA = -20 to +85 °C)
Parameter
Supply Voltage
Input Voltage
Ambient Temperature
High Level Input Voltage
Low Level Input Voltage
Output High Voltage
Symbol Min. Typ.
VCC
2.7
5.0
VI
0
TA
-20
VIH
0.7 VCC
VIL
0
VOH
2.6
Output Low Voltage
VOL
Output High Voltage
VOH
5.1
Output Low Voltage
VOL
Static Power Dissipation
Dynamic Power Dissipation
Static Current Consumption
PSTAT
PDYN
ISTAT
Dynamic Current Consumption
IDYN
1.08
2.45
Max Clk Frequency
(16XCLK) [1]
f16XCLK
Minimum Pulse Width
(IR_TXD) [2]
tmpw 1628
Pulse Width on Monoshot
(IR_TXD and IR_RXD)
tmpw 1628
Value of Pulldown Resistor used on POW- RDWN 400
460
ERDN & PULSEMOD input pins
213
237
Trigger Low Level Input Voltage
(For NRST input pin)
VIL_TRIG 0.93 0.96
2.11 2.14
Trigger High Level Input Voltage
(For NRST input pin)
VIH_TRIG 1.68 1.69
3.22 3.23
Max.
5.5
VCC
+85
VCC
0.3 VCC
Units
V
V
°C
V
V
V
0.1
V
V
0.1
V
0.61 mW
16.5 mW
50
mA
100
3
mA
3
2
MHz
Conditions
VCC = 2.7 V
IOH = 2 mA
VCC = 2.7 V
IOL = 2 mA
VCC = 5.5 V
IOH = 2 mA
VCC = 2.7 V
IOL = 2 mA
VCC = 2.7 V
VCC = 5.5 V
VCC = 2.7 V
VCC = 5.5 V
ns
ns
510
kW
260
0.98 V
2.15
1.70 V
3.25
VCC = 2.7 V
VCC = 5.5 V
VCC = 2.7 V
VCC = 5.5 V
VCC = 2.7 V
VCC = 5.5 V
Notes:
1. IrDA Parameter. The Max Clk Frequency represents the maximum clock frequency to drive the HSDL-7002’s internal state machine. Under
normal circumstances, the clock input should not exceed 16*115.2 kbit/s or 1.8432 MHz. This product can operate at higher clock rates, but the
above is the recommended rate.
2. The Maximum Pulse Width (tmpw) represents the minimum pulse width of the encoded IR_TXD pulse (and the IR_RXD pulse). As per the IrDA
Physical Layer Specification 1.4, the minimum pulse of the IR_TXD and IR_RXD pulses should be 3*(1/1.8432 MHz) or 1.63 µs.
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