HSP50214BVC View Datasheet(PDF) - Intersil
Part Name
Description
MFG CO.
'HSP50214BVC' PDF : 62 Pages View PDF
HSP50214B
CONTROL WORD 19, BITS 24-21 = 011
(3 DATA WORDS IN EACH SERIAL OUTPUT)
DATA WORD 3
DATA WORD 2
DATA WORD 1
MAGNITUDE
Q
I
DATA WORD 3
TBD
DATA WORD 2
MAGNITUDE
DATA WORD 1
Q
SEROUTA
SEROUTB
THE REMAINING CHOICES FOR THE THIRD LINK ON SEROUTB ARE:
PHASE, FREQUENCY, AGC LEVEL, AND TIMING ERROR
NOTE: Once magnitude is identified to follow Q,
it must be that way on both serial outputs.
FIGURE 35. EXAMPLE 2 SERIAL OUTPUT DATA STREAM
“NORMAL”
“INVERTED”
0
1
SERSYNC FOLLOWS LSB
0
1
“NORMAL” 1
2
SERSYNC PRECEDES MSB
“INVERTED” 1
2
LSB WORD0
MSB WORD1
MSB WORD2
2
2
3
3
MSB WORD3
2 1 0 15 14
• • • 2 1 0 15 14
•••
2 1 0 15 14 • • •
2
DATA SHIFT MSB FIRST
LSB WORD1
LSB WORD2
FIGURE 36. VALID SERSYNC CONFIGURATION OPTIONS
LATE
SERSYNC
MODE
EARLY
SERSYNC
MODE
The serial direct output can be programmed to output less
than 16-bits. New output data preempts old output data, so if
SERSYNC is programmed to precede the MSB, then data
will shift out until new data comes along. Note that if
SERSYNC is programmed to follow the LSB, then a sync will
never occur.
Buffer RAM Output Port
The Buffer RAM parallel output mode utilizes a RAM to store
output data for future retrieval by either the 8-bit
microprocessor that is configuring the PDC or by a 16-bit
baseband processing engine (which could also be a
microprocessor). Data is output from the RAM only on request
and can be obtained from either the 8-bit μP interface or from
a 16-bit interface that uses the two LSBytes of AOUT and
BOUT. The RAM holds up to eight 80-bit sample sets. Each
sample set includes 16-bits of each I, Q, magnitude, phase,
and frequency data. The RAM samples are mapped as shown
in Table 16. The Buffer RAM controller supports both FIFO
and Snapshot modes.
TABLE 16. RAM DATA STORAGE MAP
RAM
SAMPLE
SET
I
DATA
(000)
Q
DATA
(001)
|r|
DATA
(010)
Φ
DATA
(011)
F
DATA
(100)
0
I0(15:0) Q0(15:0) |r|0(15:0) φ0(15:0) f0(15:0)
1
I1(15:0) Q1(15:0) |r|1(15:0) φ1(15:0) f1(15:0)
2
I2(15:0) Q2(15:0) |r|2(15:0) φ2(15:0) f2(15:0)
3
I3(15:0) Q3(15:0) |r|3(15:0) φ3(15:0) f3(15:0)
4
I4(15:0) Q4(15:0) |r|4(15:0) φ4(15:0) f4(15:0)
5
I5(15:0) Q5(15:0) |r|5(15:0) φ5(15:0) f5(15:0)
6
I6(15:0) Q6(15:0) |r|6(15:0) φ6(15:0) f6(15:0)
7
I7(15:0) Q7(15:0) |r|7(15:0) φ7(15:0) f7(15:0)
NOTE: I and Q are sample aligned in time. |r| and φ are sample
aligned in time, but one sample delayed from I or Q. The
frequency sample is delayed in time from I or Q by 1
sample time + 63 tap FIR impulse response. If the FIR is
set to decimate, the FIR output will be repeated every
sample time until a new value appears at the filter output.
(i.e., the frequency samples are clocked out at the I, Q
sample rate regardless of decimation.)
37
FN4450.4
May 1, 2007
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