HT47C20 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT47C20' PDF : 56 Pages View PDF
Stack register - STACK
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into four levels and is neither part of
the data nor part of the program space, and is neither
readable nor writeable. The activated level is indexed by
the stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt acknowledg-
ment, the contents of the program counter are pushed
onto the stack. At the end of a subroutine or an interrupt
routine, signaled by a return instruction (RET or RETI),
the program counter is restored to its previous value
from the stack. After a chip reset, the SP will point to the
top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is sub-
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent four return ad-
dresses are stored).
Data memory - RAM
The data memory is designed with 83 ´ 8 bits. The data
memory and is divided into two functional groups: spe-
cial function registers and general purpose data mem-
ory (64´ 8). Most are read/write, but some are read only.
The special function registers include the indirect ad-
dressing register 0 (00H), the memory pointer register 0
(mp0; 01H), the indirect addressing register 1 (02H), the
memory pointer register 1 (MP1;03H), the bank pointer
(BP;04H), the accumulator (ACC;05H), the program
counter lower-order byte register (PCL;06H), the table
pointer (TBLP;07H), the table higher-order byte register
(TBLH;08H), the real time clock control register
(RTCC;09H), the status register (STATUS;0AH), the in-
terrupt control register 0 (INTC0;0BH), the I/O registers
(PA;12H, PB;14H), the interrupt control register 1
(INTC1;1EH), the Timer/Event Counter A higher order
byte register (TMRAH; 20H), the Timer/Event Counter A
lower order byte register (TMRAL; 21H), the timer/event
counter control register (TMRC; 22H), the Timer/Event
Counter B higher order byte register (TMRBH; 23H), the
Timer/Event Counter B lower order byte register (TMRBL;
24H), and the RC oscillator type A/D converter control reg-
ister (ADCR; 25H). The remaining space before the 40H
are reserved for future expanded usage and reading
these location will return the result 00H. The general
purpose data memory, addressed from 40H to 7FH, is
used for data and control information under instruction
command.
HT47C20
0 0 H In d ir e c t A d d r e s s in g R e g is te r 0
01H
MP 0
0 2 H In d ir e c t A d d r e s s in g R e g is te r 1
03H
M P1
04H
BP
05H
ACC
06H
PCL
07H
TB LP
08H
TB LH
09H
R TC C
0A H
STATU S
0B H
IN T C 0
0C H
0D H
0E H
0.H
10H
11H
12H
PA
13H
14H
PB
15H
16H
17H
18H
19H
1A H
1B H
1C H
1D H
1E H
IN T C 1
1.H
20H
TM R AH
21H
TM R AL
22H
TM R C
23H
TM R BH
24H
TM R BL
25H
ADCR
26H
40H
S p e c ia l P u r p o s e
D a ta M e m o ry
:U nused
R e a d a s "0 0 "
G e n e ra l P u rp o s e
D a ta M e m o ry
(6 4 B y te s )
7.H
RAM mapping (bank 0)
All data memory areas can handle arithmetic, logic,
increment, decrement and rotate operations. Except
for some dedicated bits, each bit in the data memory
can be set and reset by the SET [m].i and CLR [m].i
instruction, respectively. They are also indirectly ac-
cessible through memory pointer registers
(MP0;01H, MP1;03H).
Rev. 1.60
10
July 26, 2002
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