HT47C20 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT47C20' PDF : 56 Pages View PDF
HT47C20
Functional Description
Execution flow
The system clock for the HT47C20 is derived from either
a crystal or an RC oscillator. The system clock is inter-
nally divided into four non-overlapping clocks. One in-
struction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction
to effectively execute in one cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
Program counter - PC
The 11-bit program counter (PC) controls the sequence
in which the instructions stored in the program ROM are
executed and its contents specify a maximum of 2048
addresses.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to get the proper instruction. Otherwise
proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
When a control transfer takes place, an additional
dummy cycle is required.
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
S y s te m C lo c k
In s tr u c tio n C lo c k
PC
PC
PC +1
PC +2
. e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
. e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
Execution flow
. e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Mode
Initial Reset
External Interrupt
Time Base Interrupt
RTC Interrupt
Timer/event Counter Interrupt
Skip
Loading PCL
Jump, Call Branch
Return from Subroutine
*10 *9
0
0
0
0
0
0
0
0
0
0
*10 *9
#10 #9
S10 S9
Program Counter
*8 *7 *6 *5 *4 *3 *2 *1 *0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
PC+2
*8 @7 @6 @5 @4 @3 @2 @1 @0
#8 #7 #6 #5 #4 #3 #2 #1 #0
S8 S7 S6 S5 S4 S3 S2 S1 S0
Note: *10~*0: Program counter bits
S10~S0: Stack register bits
Program counter
#10~#0: Instruction code bits
@7~@0: PCL bits
Rev. 1.60
8
July 26, 2002
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