HT47C20L View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT47C20L' PDF : 55 Pages View PDF
V DD
W EAK
P u ll- u p
R e a d D a ta
D a ta B u s
P B 0~P B 3
PB Input Lines
D a ta B u s
W r ite
C h ip R e s e t
R e a d I/O
S y s te m W a k e -u p
D
Q
CK
S
Q
HT47C20L
V DD
M ask
O p tio n
V DD
W EAK
P u ll- u p
M a s k O p tio n
PA2
M a s k O p tio n
PA2 Input/Output Lines
LCD Display Memory
The HT47C20L provides an area of embedded data
memory for LCD display. The LCD display memory is
designed into 20´4 bits. If the LCD selected 19´4 seg-
ments output, the 53H of the LCD display memory can
not be accessed. This area is located from 40H to 53H
of the RAM at Bank 1. Bank pointer (BP; located at 04H
of the data memory) is the switch between the general
data memory and the LCD display memory. When the
BP is set ²1² any data written into 40H~53H will effect
the LCD display (indirect addressing mode using MP1).
When the BP is cleared ²0², any data written into
40H~53H has to access the general purpose data mem-
ory. The LCD display memory can be read and written
only by indirect addressing mode using MP1. When
data is written into the display data area, it is automati-
cally read by the LCD driver which then generates the
corresponding LCD driving signals. To turn the display
On or Off, a ²1² or a ²0² is written to the corresponding
bit of the display memory, respectively.
The figure illustrates the mapping between the display
memory and LCD pattern for the HT47C20L.
LCD Driver Output
The output number of the HT47C20L LCD driver can be
20´2 or 20´3 or 19´4 by mask option (i.e.1/2 duty, 1/3
duty or 1/4 duty).
The bias type LCD driver is ²C² type. If the 1/2 duty or
1/3 duty type is selected, the 1/2 bias type is selected. If
the 1/4 duty type is selected, the 1/3 bias type is se-
lected. A capacitor has to be connected between C1 and
C2. The two kinds of the configurations of V1, V2 and V3
pins are as follows:
C1
C2
V1
V2
V3
V DD
V1, V2, V3 Application Diagram
COM
40H 41H 42H 43H
51H 52H 53H
B it
0
0
1
1
2
2
3
3
SEG M ENT
0
1
2
3
17
18
19
Display Memory (Bank 1)
Rev. 2.30
23
December 2, 2005
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