HT49CA1 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT49CA1' PDF : 58 Pages View PDF
HT49RA1/HT49CA1
For the 16-bit Timer/Event Counter which has both low
byte and high byte timer registers, accessing these reg-
isters is carried out in a specific way. It must be noted
when using instructions to preload data into the low byte
timer register, namely TMR1L, the data will only be
placed in a low byte buffer and not directly into the low
byte timer register. The actual transfer of the data into
the low byte timer register is only carried out when a
write to its associated high byte timer register, namely
TMR1H, is executed. On the other hand, using instruc-
tions to preload data into the high byte timer register will
result in the data being directly written to the high byte
timer register. At the same time the data in the low byte
buffer will be transferred into its associated low byte
timer register. For this reason, the low byte timer register
should be written first when preloading data into the
16-bit timer registers. It must also be noted that to read
the contents of the low byte timer register, a read to the
high byte timer register must be executed first to latch
the contents of the low byte timer register into its associ-
ated low byte buffer. After this has been done, the low
byte timer register can be read in the normal way. Note
that reading the low byte timer register will result in read-
ing the previously latched contents of the low byte buffer
and not the actual contents of the low byte timer register.
Timer Control Registers - TMR0C, TMR1C
The flexible features of the Holtek microcontroller
Timer/Event Counters enable them to operate in three
different modes, the options of which are determined by
the contents of their respective control register.
It is the Timer Control Register together with its corre-
sponding timer registers that control the full operation of
the Timer/Event Counters. Before the timers can be
used, it is essential that the appropriate Timer Control
Register is fully programmed with the right data to en-
sure its correct operation, a process that is normally car-
ried out during program initialisation.
To choose which of the three modes the timer is to oper-
ate in, either in the timer mode, the event counting mode
or the pulse width measurement mode, bits 7 and 6 of
the Timer Control Register, which are known as the bit
P r e s c a le r O u tp u t
pair T0M1/T0M0 or T1M1/T1M0 respectively, depend-
ing upon which timer is used, must be set to the required
logic levels. The timer-on bit, which is bit 4 of the Timer
Control Register and known as T0ON or T1ON, depend-
ing upon which timer is used, provides the basic on/off
control of the respective timer. Setting the bit high allows
the counter to run, clearing the bit stops the counter. If
the timer is in the event count or pulse width measure-
ment mode, the active transition edge level type is se-
lected by the logic level of bit 3 of the Timer Control
Register which is known as T0E or T1E depending upon
which timer is used.
Configuring the Timer Mode
In this mode, the timer can be utilized to measure fixed
time intervals, providing an internal interrupt signal each
time the counter overflows. To operate in this mode, the
bit pair, T0M1/T0M0 or T1M1/T1M0 depending upon
which timer is used, must be set to 1 and 0 respectively.
In this mode the internal clock is used as the timer clock.
The timer-on bit, T0ON or T1ON, depending upon which
timer is used, must be set high to enable the timer to run.
Each time an internal clock high to low transition occurs,
the timer increments by one; when the timer is full and
overflows, an interrupt signal is generated and the timer
will preload the value already loaded into the preload
register and continue counting. A timer overflow condi-
tion and corresponding internal interrupt is one of the
wake-up sources, however, the internal interrupts can
be disabled by ensuring that the ET0I or ET1I bits of the
INTC0, INTC1 register are reset to zero.
Configuring the Event Counter Mode
In this mode, a number of externally changing logic
events, occurring on the external timer pin, can be re-
corded by the internal timer. For the timer to operate in
the event counting mode, the bit pair, T0M1/T0M0 or
T1M1/T1M0 depending upon which timer is used, must
be set to 0 and 1 respectively. The timer-on bit T0ON or
T1ON depending upon which timer is used, must be set
high to enable the timer to count. Depending upon which
counter is used, if T0E or T1E is low, the counter will in-
crement each time the external timer pin receives a low
In c re m e n t
T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
Timer Mode Timing Chart
T im e r + N
T im e r + N + 1
E x te rn a l E v e n t
In c re m e n t
T im e r C o u n te r
Rev. 1.10
T im e r + 1
T im e r + 2
Event Counter Mode Timing Chart
25
T im e r + 3
March 30, 2014
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