HT49RA1 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT49RA1' PDF : 58 Pages View PDF
HT49RA1/HT49CA1
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer in-
terrupt enable bit, ET0I, ET1I must first be set. An actual
Timer/Event Counter interrupt will take place when the
relevant Timer/Event Counter request flag, T0F, T1F is
set, a situation that will occur when the relevant
Timer/Event Counter overflows. When the interrupt is en-
abled, the stack is not full and a Timer/Event Counter
overflow occurs, a subroutine call to the timer interrupt
vector at location 0CH, 10H, will take place. When the in-
terrupt is serviced, the timer interrupt request flag, T0F,
T1F will be automatically reset and the EMI bit will be au-
tomatically cleared to disable other interrupts.
Time Base Interrupt
For a Time Base interrupt to occur the the global inter-
rupt enable bit, EMI, and the corresponding internal in-
terrupt enable bit, which is bit 1 of the INTC1 register,
known as ETBI, must be first set. An actual Time Base
interrupt will be generated when the Time Base interrupt
request flag is set which is bit 5 of the INTC1 register
and known as TBF. This will occur when when a time-out
signal is generated from the Time Base. When the mas-
ter interrupt global enable bit is set, the stack is not full
and the corresponding Time Base interrupt enable bit is
set, an internal Time Base interrupt will be generated
when a time-out signal is generated from the Time Base.
This will create a subroutine call to location 014H. When
a Time Base interrupt occurs, the EMI bit will be cleared
to disable other interrupts. The purpose of the Time
Base interrupt is to provide an interrupt signal at fixed
time periods. The Time Base interrupt clock source orig-
inates from the internal clock source fS. This fS input
clock first passes through a divider, the division ratio of
which is selected by configuration options to provide
longer Time Base interrupt periods. The Time Base in-
terrupt time-out period ranges from 212/fS~215/fS. The
clock source that generates fS, which in turn controls the
Time Base interrupt period, can originate from three dif-
ferent sources, the RTC oscillator, Watchdog Timer os-
cillator or the System oscillator/4, the choice of which is
determine by the fS clock source configuration option.
Real Time Clock Interrupt
For a Real Time Clock interrupt to occur the global inter-
rupt enable bit, EMI, and the corresponding internal in-
terrupt enable bit, which is bit 2 of the INTC1 register,
known as ERTI, must be first set. An actual Real Time
Clock interrupt will be generated when the Real Time
Clock interrupt request flag is set which is bit 6 of the
INTC1 register and known as RTF. When the master in-
terrupt global enable bit is set, the stack is not full and
the corresponding Real Time Clock interrupt enable bit
is set, an internal Real Time Clock interrupt will be gen-
erated when a time-out signal occurs, a subroutine call
to location 018H will be created. When a Real Time in-
terrupt occurs, the EMI bit will be cleared to disable
other interrupts.
Similar in operation to the Time Base interrupt, the pur-
pose of the RTC interrupt is also to provide an interrupt
signal at fixed time periods. The RTC interrupt clock
source originates from the internal clock source fS. This
fS input clock first passes through a divider, the division
ratio of which is selected by programming the appropri-
ate bits in the RTCC register to obtain longer RTC inter-
rupt periods whose value ranges from 28/fS~215/fS. The
clock source that generates fS, which in turn controls the
RTC interrupt period, can originate from three different
sources, the RTC oscillator, Watchdog Timer oscillator
or the System oscillator/4, the choice of which is deter-
mine by the fS clock source configuration option. Note
that if the RTC oscillator is selected as the system clock,
then fS, and correspondingly the RTC interrupt, will also
have the RTC oscillator as its clock source.
fS Y S /4
W D T O s c illa to r
R T C O s c illa to r
fS S o u rc e
C o n fig u r a tio n
O p tio n
fS
C o n fig u r a tio n O p tio n
D iv id e b y 2 1 2 ~ 2 1 5
Time Base Interrupt
T im e B a s e In te r r u p t
2 12/fS ~ 2 15/fS
Rev. 1.10
fS Y S /4
W D T O s c illa to r
R T C O s c illa to r
fS S o u rc e
C o n fig u r a tio n
fS
O p tio n
D iv id e b y 2 8 ~ 2 1 5
(S e t b y R T C C
R e g is te r s )
R T2~R T0
RTC Interrupt
32
R T C In te rru p t
2 8/fS ~ 2 15/fS
March 30, 2014
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