HT49RA1 View Datasheet(PDF) - Holtek Semiconductor

Part Name

Description

MFG CO.

HT49RA1

Remote Type 8-Bit MCU with LCD

Holtek Semiconductor 

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HT49RA1/HT49CA1

A u to m a tic a lly C le a r e d b y IS R

M a n u a lly S e t o r C le a r e d b y S o ftw a r e

A u to m a tic a lly D is a b le d b y IS R

C a n b e E n a b le d M a n u a lly

P r io r ity

E x te rn a l In te rru p t

E E I0

EM I

H ig h

R e q u e s t F la g E IF 0

E x te rn a l In te rru p t

E E I1

R e q u e s t F la g E IF 1

T im e r /E v e n t C o u n te r 0

E T0I

In te r r u p t R e q u e s t F la g T 0 F

T im e r /E v e n t C o u n te r 1

E T1I

In te r r u p t R e q u e s t F la g T 1 F

T im e B a s e

ETBI

In te r r u p t R e q u e s t F la g T B F

R e a l T im e C lo c k

In te r r u p t R e q u e s t F la g R T F

ER TI

Low

Interrupt Structure

In te rru p t

P o llin g

Note that the RTC interrupt period is controlled by both

configuration options and an internal register RTCC. A

configuration option selects the source clock for the in-

ternal clock fS, and the RTCC register bits RT2, RT1 and

RT0 select the division ratio. Note that the actual divi-

sion ratio can be programmed from 28 to 215. For details

of the actual RTC interrupt periods, consult the RTCC

register section.

Note after a wake-up the system requires 1024 clock cy-

cles to resume normal operation.

Programming Considerations

By disabling the interrupt enable bits, a requested inter-

rupt can be prevented from being serviced, however,

once an interrupt request flag is set, it will remain in this

condition in the INTC0, INTC1 registers until the corre-

sponding interrupt is serviced or until the request flag is

cleared by a software instruction.

It is recommended that programs do not use the ²CALL

subroutine² instruction within the interrupt subroutine.

Interrupts often occur in an unpredictable manner or

need to be serviced immediately in some applications. If

only one stack is left and the interrupt is not well con-

trolled, the original control sequence will be damaged

once a ²CALL subroutine² is executed in the interrupt

subroutine.

All of these interrupts have the capability of waking up

the processor when in the Power Down Mode.

Only the Program Counter is pushed onto the stack. If

the contents of the register or status register are altered

by the interrupt service program, which may corrupt the

desired control sequence, then the contents should be

saved in advance.

Rev. 1.10

33

March 30, 2014

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