HT56R26 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT56R26' PDF : 134 Pages View PDF
HT56R22/HT56R23/HT56R24/HT56R25/HT56R26
The START bit in the register is used to start and reset
the A/D converter. When themicrocontroller sets this bit
from low to high and then low again, an analog to digital
conversion cycle will be initiated. When the START bit is
brought from low to high but not low again, the EOCB bit
in the ADCR register will be set to a ²1² and the analog
to digital converter will be reset. It is the START bit that is
used to control the overall start operation of the internal
analog to digital converter.
The EOCB bit in the ADCR register is used to indicate
when the analog to digital conversion process is com-
plete. This bit will be automatically set to ²0² by the
microcontroller after a conversion cycle has ended. In
addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the inter-
rupts are enabled, an appropriate internal interrupt sig-
nal will be generated. This A/D internal interrupt signal
will direct the program flow to the associated A/D inter-
nal interrupt address for processing. If the A/D internal
interrupt is disabled, the microcontroller can be used to
poll the EOCB bit in the ADCR register to check whether
it has been cleared as an alternative method of detect-
ing the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates
from the system clock fSYS, is first divided by a division
ratio, the value of which is determined by the ADCS2,
ADCS1 and ADCS0 bits in the ACSR register.
Controlling the power on/off function of the A/D con-
verter circuitry is implemented using the value of the
ADONB bit.
Although the A/D clock source is determined by the sys-
tem clock fSYS, and by bits ADCS2, ADCS1 and ADCS0,
there are some limitations on the maximum A/D clock
source speed that can be selected. As the minimum value
of permissible A/D clock period, tAD, is 0.5ms, care must be
taken for system clock speeds in excess of 4MHz. For
system clock speeds in excess of 4MHz, the ADCS2,
ADCS1 and ADCS0 bits should not be set to ²000². Doing
so will give A/D clock periods that are less than the mini-
mum A/D clock period which may result in inaccurate A/D
conversion values. Refer to the following table for exam-
ples, where values marked with an asterisk * show where,
depending upon the device, special care must be taken,
as the values may be less than the specified minimum A/D
Clock Period.
A/D Input Pins
All of the A/D analog input pins are pin-shared with the
I/O pins on Port A. Bits PCR7~PCR0 in the ADPCR reg-
ister, determine whether the input pins are setup as nor-
mal Port A input/output pins or whether they are setup as
analog inputs. In this way, pins can be changed under
program control to change their function from normal I/O
operation to analog inputs and vice versa. Pull-high resis-
tors, which are setup through register programming, ap-
ply to the input pins only when they are used as normal
I/O pins, if setup as A/D inputs the pull-high resistors will
be automatically disconnected. Note that it is not neces-
sary to first setup the A/D pin as an input in the PAC port
control register to enable the A/D input as when the
PCR7~PCR0 bits enable an A/D input, the status of the
port control register will be overridden.
fSYS
1MHz
ADCS2,
ADCS1,
ADCS0=000
(fSYS/2)
2ms
ADCS2,
ADCS1,
ADCS0=001
(fSYS/8)
8ms
A/D Clock Period (tAD)
ADCS2,
ADCS1,
ADCS0=010
(fSYS/32)
ADCS2,
ADCS1,
ADCS0=100
(fSYS)
ADCS2,
ADCS1,
ADCS0=101
(fSYS/4)
32ms
1ms
4ms
ADCS2,
ADCS1,
ADCS0=110
(fSYS/16)
16ms
ADCS2,
ADCS1,
ADCS0=011,
111
Undefined
2MHz
1ms
4ms
16ms
500ns
2ms
8ms
Undefined
4MHz
500ns
2ms
8ms
250ns*
1ms
4ms
Undefined
8MHz
250ns*
1ms
4ms
125ns*
500ns
2ms
Undefined
12MHz 167ns*
667ns
2.67ms
83ns*
333ns*
1ms
Undefined
A/D Clock Period Examples
Rev. 1.30
63
December 26, 2014
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