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HT56R26 View Datasheet(PDF) - Holtek Semiconductor

Part Name
Description
MFG CO.
HT56R26
Holtek
Holtek Semiconductor Holtek
'HT56R26' PDF : 134 Pages View PDF
HT56R22/HT56R23/HT56R24/HT56R25/HT56R26
SIM0 SIM1 SIM2
SPI Master/Slave Clock
Control and I2C Enable
0
0
0 SPI Master, fSYS/4
0
0
1 SPI Master, fSYS/16
0
1
0 SPI Master, fSYS/64
0
1
1 SPI Master, fSUB
1
0
0
SPI Master Timer/Event
Counter 0 output/2
1
0
1 SPI Slave
1
1
0 I2C mode
1
1
0 Not used
SPI Control Register - SIMCTL2
The SIMCTL2 register is also used by the I2C interface
but has the name SIMAR.
· TRF
The TRF bit is the Transmit/Receive Complete flag and
is set high automatically when an SPI data transmis-
sion is completed, but must be cleared by the applica-
tion program. It can be used to generate an interrupt.
· WCOL
The WCOL bit is used to detect if a data collision has
occurred. If this bit is high it means that data has been
attempted to be written to the SIMDR register during a
data transfer operation. This writing operation will be
ignored if data is being transferred. The bit can be
cleared by the application program. Note that using
the WCOL bit can be disabled or enabled via configu-
ration option.
· CSEN
The CSEN bit is used as an on/off control for the SCS
pin. If this bit is low then the SCS pin will be disabled
and placed into a floating condition. If the bit is high
the SCS pin will be enabled and used as a select pin.
Note that using the CSEN bit can be disabled or en-
abled via configuration option.
· MLS
This is the data shift select bit and is used to select
how the data is transferred, either MSB or LSB first.
Setting the bit high will select MSB first and low for
LSB first.
· CKEG and CKPOL
These two bits are used to setup the way that the
clock signal outputs and inputs data on the SPI bus.
These two bits must be configured before data trans-
fer is executed otherwise an erroneous clock edge
may be generated. The CKPOL bit determines the
base condition of the clock line, if the bit is high then
the SCK line will be low when the clock is inactive.
When the CKPOL bit is low then the SCK line will be
high when the clock is inactive. The CKEG bit deter-
mines active clock edge type which depends upon the
condition of CKPOL.
CKPOL
0
CKEG
0
0
1
1
0
1
1
SCK Clock Signal
High Base Level
Active Rising Edge
High Base Level
Active Falling Edge
Low Base Level
Active Falling Edge
Low Base Level
Active Rising Edge
SPI Communication
After the SPI interface is enabled by setting the SIMEN
bit high, then in the Master Mode, when data is written to
the SIMDR register, transmission/reception will begin si-
multaneously. When the data transfer is complete, the
TRF flag will be set automatically, but must be cleared
using the application program. In the Slave Mode, when
the clock signal from the master has been received, any
data in the SIMDR register will be transmitted and any
data on the SDI pin will be shifted into the SIMDR regis-
ter. The master should output an SCS signal to enable
the slave device before a clock signal is provided and
slave data transfers should be enabled/disabled be-
fore/after an SCS signal is received.
The SPI will continue to function even after a HALT in-
struction has been executed.
I2C Interface
The I2C interface is used to communicate with external
peripheral devices such as sensors, EEPROM memory
etc. Originally developed by Philips, it is a two line low
speed serial interface for synchronous serial data trans-
fer. The advantage of only two lines for communication,
relatively simple communication protocol and the ability
to accommodate multiple devices on the same bus has
made it an extremely popular interface type for many
applications.
· I2C Interface Operation
The I2C serial interface is a two line interface, a serial
data line, SDA, and serial clock line, SCL. As many
devices may be connected together on the same bus,
their outputs are both open drain types. For this rea-
son it is necessary that external pull-high resistors are
connected to these outputs. Note that no chip select
line exists, as each device on the I2C bus is identified
by a unique address which will be transmitted and re-
ceived on the I2C bus.
When two devices communicate with each other on
the bidirectional I2C bus, one is known as the master
device and one as the slave device. Both master and
slave can transmit and receive data, however, it is the
master device that has overall control of the bus. For
these devices, which only operates in slave mode,
there are two methods of transferring data on the I2C
bus, the slave transmit mode and the slave receive
mode.
Rev. 1.30
70
December 26, 2014
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