HT56R666 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT56R666' PDF : 104 Pages View PDF
HT56R66/HT56R666
System Operating Modes
The devices have the ability to operate in several differ-
ent modes. This range of operating modes, known as
Normal Mode, Slow Mode, Idle Mode and Sleep Mode,
allow the devices to run using a wide range of different
slow and fast clock sources. The devices also possess
the ability to dynamically switch between different clocks
and operating modes. With this choice of operating
functions users are provided with the flexibility to ensure
they obtain optimal performance from the device ac-
cording to their application specific requirements.
Clock Sources
In discussing the system clocks for the devices, they
can be seen as having a dual clock mode. These dual
clocks are what are known as a High Oscillator and the
other as a Low Oscillator. The High and Low Oscillator
are the system clock sources and can be selected dy-
namically using the HLCLK bit in the CLKMOD register.
The High Oscillator has the internal name fM whose
source is selected using a configuration option from a
choice of either an external crystal/resonator, external
RC oscillator or external clock source.
The Low Oscillator clock source, has the internal name
fSL, whose source is also selected by configuration op-
tion from a choice of either an external 32768Hz oscilla-
tor or the internal 32K_INT oscillator. This internal fSL, fM
clock, is further modified by the SLOWC0~SLOWC2
bits in the CLKMOD register to provide the low fre-
quency clock source fSLOW.
An additional sub internal clock, with the internal name
fSUB, is a 32kHz clock source which can be sourced from
either the internal 32K_INT oscillator or an external
32768 Hz crystal, selected by configuration option. To-
gether with fSYS/4, it is used as a clock source for certain
internal functions such as the LCD driver, Watchdog
Timer, Buzzer, RTC Interrupt and Time Base Interrupt.
The LCD clock source is the fSUB clock source divided by
8, giving a frequency of 4kHz. The internal clock fS, is
simply a choice of either fSUB or fSYS/4, using a configura-
tion option.
Operating Modes
After the correct clock source configuration selections
are made, overall operation of the chosen clock is
achieved using the CLKMOD register. A combination of
the HLCLK and IDLEN bits in the CLKMOD register and
use of the HALT instruction determine in which mode the
device will be run. The devices can operate in the follow-
ing Modes.
· Normal Mode
fM on, fSLOW on, fSYS=fM, CPU on, fS on, fLCD on/off de-
pending upon the LCDEN bit, fWDT on/off depending
upon the WDT configuration option and WDT control
register.
· Slow Mode0
fM off, fSLOW=32K_INT oscillator or the 32768Hz oscil-
lator, fSYS=fSLOW, CPU on, fS on, fLCD on/off depending
upon the LCDEN bit, fWDT on/off depending upon the
WDT configuration option and WDT control register.
b7
b0
S L O W C 2 S L O W C 1 S L O W C 0 S IM ID L E L T O H T O ID L E N H L C L K C L K M O D R e g is te r
fS Y S s e le c t
1 : fM
0 : fS L O W
Id le m o d e
1 : e n a b le
0 : d is a b le
H ig h o s c illa to r r e a d y fla g
1 : tim e - o u t
0 : n o n - tim e - o u t
L o w o s c illa to r r e a d y fla g
1 : tim e - o u t
0 : n o n - tim e - o u t
S P I/I2 C c o n tin u e s r u n n in g in Id le m o d e
1 :e n a b le
0 :d is a b le
fS L O W s e le c tio n
S L O W W C 2 S L O W W C 1 S L O W W C 0 fS L O W
0
0
0
fS L
0
0
1
fS L
0
1
0
fM /6 4
0
1
1
fM /3 2
1
0
0
fM /1 6
1
0
1
fM /8
1
1
0
fM /4
1
1
1
fM /2
Clock Control Register - CLKMOD
Rev. 1.40
80
May 11, 2012
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