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ICS1893BFILF View Datasheet(PDF) - Integrated Device Technology

Part Name
Description
MFG CO.
ICS1893BFILF
IDT
Integrated Device Technology IDT
'ICS1893BFILF' PDF : 138 Pages View PDF
ICS1893BF Data Sheet Rev. E - Release
Chapter 9 DC and AC Operating Conditions
9.5.2 Timing for Transmit Clock (TXCLK) Pins
Table 9-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various
interfaces. Figure 9-3 shows the timing diagram for the time periods.
Table 9-9. Transmit Clock Timing
Time
Period
Parameter
t1 TXCLK Duty Cycle
t2a TXCLK Period
t2b TXCLK Period
Conditions
100M MII (100Base-TX)
10M MII (10Base-T)
Min. Typ. Max. Units
35 50 65 %
– 40 – ns
– 400 – ns
Figure 9-3. Transmit Clock Timing Diagram
t1
TXCLK
t2x
ICS1893BF, Rev. E, 8/11/09
Copyright © 2009, IDT, Inc.
All rights reserved.
111
August, 2009
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