ICS1893BFILF View Datasheet(PDF) - Integrated Device Technology
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Description
MFG CO.
'ICS1893BFILF' PDF : 138 Pages View PDF
ICS1893BF Data Sheet - Release
Chapter 9 DC and AC Operating Conditions
9.5.3 Timing for Receive Clock (RXCLK) Pins
Table 9-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various
interfaces. Figure 9-4 shows the timing diagram for the time periods.
Table 9-10. MII Receive Clock Timing
Time
Period
Parameter
t1 RXCLK Duty Cycle
t2a RXCLK Period
t2b RXCLK Period
Conditions
–
100M MII (100Base-TX)
10M MII (10Base-T)
Min. Typ. Max. Units
35 50 65 %
– 40 –
ns
– 400 –
ns
Figure 9-4. Receive Clock Timing Diagram
t1
RXCLK
t2
ICS1893BF, Rev. E, 8/11/09
Copyright © 2009, IDT, Inc.
All rights reserved.
112
August, 2009
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