ICS525-03
PECL Input OSCaR™ User Configurable Clock
Pin Assignment
R5
R6
S0
S1
S2
VDD
PECL
PECLIN
GND
V0
V1
V2
V3
V4
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
28-pin SSOP
R4
R3
R2
R1
R0
VDD
CLK2
CLK1
GND
RES
V8
V7
V6
V5
RES Value Table
RES
CLK1 CLK2 Pre-divide (P)
0
CMOS CMOS
2
1.1 kΩ Resistor PECL PECL
1
to VDD
Output Divider and Maximum Output Frequency Table
S0
pin 5
0
0
0
0
1
1
1
1
S1
pin 4
0
0
1
1
0
0
1
1
S2
CLK
Max. Output Frequency (MHz)
pin 3 Output Divider
VDD = 5 V
VDD = 3.3 V
(OD)
RES = 0 RES = 1.1 kΩ RES = 0 RES = 1.1 kΩ
0
6
67
34
40
20
1
2
200
100
120
60
0
8
50
25
30
15
1
4
100
50
60
30
0
5
80
40
48
24
1
7
57
29
34
17
0
1
250
200
200
125
1
3
133
80
80
40
Note: 0 = connect directly to ground; 1 = connect directly to VDD.
MDS 525-03 H
2
Revision 010906
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com