ICS525R-03ILF View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS525R-03ILF' PDF : 7 Pages View PDF
ICS525-03
PECL Input OSCaR™ User Configurable Clock
Pin Descriptions
Pin
Pin
Number Name
1, 2,
24-28
R5, R6,
R0-R4
3, 4, 5 S0, S1, S2
6, 23
VDD
7
PECLIN
8
PECLIN
9, 20
GND
10 - 18 V0 - V8
19
RES
21
CLK1
22
CLK2
Pin
Type
I(PU)
I(PU)
Power
Input
Input
Power
I(PU)
Input
Output
Output
Pin Description
Reference divider word input pins determined by user. Forms a binary
number from 0 to 127.
Select pins for output divider determined by user. See table above.
Connect to VDD.
PECL input.
Complementary PECL input.
Connect to ground.
VCO divider word input pins determined by user. Forms a binary number from
0 to 511.
Select eithe PECL or CMOS outputs. See table above.
Output clock. Either PECL or CMOS determined by RES.
Output clock. Either PECL or CMOS determined by RES.
KEY: I(PU) = Input with internal pull-up resistor.
Output Clock Selection
If RES is connected directly to ground, CLK1 and CLK2 are low skew, CMOS outputs clocks. They are not
complementary. If RES is connected to VDD through a 1.1 kΩ resistor, then CLK1 and CLK2 become
complementary PECL outputs which require the external resistor network shown in the the block diagram. Refer to
Application Note MAN09 for additional information.
MDS 525-03 H
3
Revision 010906
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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