Qdatasheet_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

ICS580M-01T View Datasheet(PDF) - Integrated Circuit Systems

Part Name
Description
MFG CO.
ICS580M-01T
ICST
Integrated Circuit Systems ICST
'ICS580M-01T' PDF : 6 Pages View PDF
1 2 3 4 5 6
ICS580-01
Glitch-Free Clock Multiplexer
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS
Minimum
Supply voltage, VDD
Referenced to GND
Inputs and Clock Outputs
Referenced to GND
-0.5
Ambient Operating Temperature
0
Ambient Operating Temperature, I version
Industrial temperature
-40
Soldering Temperature
Max of 10 seconds
Storage temperature
-65
DC CHARACTERISTICS (VDDC = VDDI = 3.3 V unless noted)
Operating Voltage, VDDC
2.5
Operating Voltage, VDDI
VDDC
Input High Voltage, VIH, note 3
INA and INB only
(VDDC/2)+1
Input Low Voltage, VIL, note 3
INA and INB only
Input High Voltage, VIH
Non-clock inputs
2
Input Low Voltage, VIL
Non-clock inputs
Output High Voltage, VOH
IOH=-12mA
VDDC-0.5
Output Low Voltage, VOL
IOL=12mA
Operating Supply Current, IDD
50 MHz inputs, no load
Short Circuit Current
On-chip pull-up resistor, non-clock inputs
Pull-up to VDDC
Input Capacitance
AC CHARACTERISTICS (VDDC = VDDI = 3.3 V unless noted)
Input Frequency, INA and INB. Note 1.
VDDC = 5 V
1/timeout
VDDC = 3.3 V
1/timeout
VDDC = 2.7 V
1/timeout
Propagation Delay, INA or INB to output
VDDC = 5 V
VDDC = 3.3 V
VDDC = 2.7 V
Transition Detector Timeout, DIV=0
VDDI = 5 V
175
VDDI = 3.3 V
500
VDDI = 2.7 V
750
Transition Detector Timeout, DIV=1
VDDI = 5 V
20
VDDI = 3.3 V
55
VDDI = 2.7 V
100
Output Clock Rise Time
Output Clock Fall Time
Output Clock Skew, CLK1 to CLK2
Note 2
-250
Typical
VDDC/2
VDDC/2
6
±70
250
4
4
5
6
350
1000
1500
40
110
200
0
Maximum
7
VDD+0.5
70
85
260
150
5.5
5.5
VDDI
(VDDC/2)-1
VDDC
0.8
0.5
270
220
180
8
10
12
700
2000
3000
80
210
400
1.5
1.5
250
Units
V
V
°C
°C
°C
°C
V
V
V
V
V
V
V
V
mA
mA
k
pF
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
Note 1. Frequencies less than the minimum may cause a timeout, which will not guarantee glitch-free switching unless the clock is
actually stopped.
Note 2. Assumes identically loaded outputs with identical rise times, measured at VDD/2.
Note 3. Output duty cycle is set by duty cycle of input clock at VDDC/2.
MDS 580-01 A
5
Revision 030300
Printed 11/28/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
Share Link: GO URL

All Rights Reserved © qdatasheet.com  [ Privacy Policy ] [ Contact Us ]