LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-
3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8531-01 is a low skew, high performance
ICS
1-to-9 Differential-to-3.3V LVPECL Fanout Buffe
HiPerClockS™ and a member of the HiPerClockS™ family of High
Perfor mance Clock Solutions from IDT. The
ICS8531-01 has two selectable clock inputs. The
CLK, nCLK pair can accept most standard differential input
levels. The PCLK, nPCLK pair can accept LVPECL, CML, or
SSTL input levels. The clock enable is internally synchronized
to eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output skew and part-to-part skew character-
istics make the ICS8531-01 ideal for high performance work-
station and server applications.
ICS8531-01
FEATURES
• Nine differential 3.3V LVPECL outputs
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 500MHz
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to 3.3V LVPECL levels with resistor bias on nCLK input
• Additive phase jitter, RMS: 0.17ps (typical)
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 2ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
• Industrial Temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_EN
D
Q
LE
CLK
nCLK
0
Q0
PCLK
nPCLK
1
nQ0
Q1
nQ1
CLK_SEL
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
32 31 30 29 28 27 26 25
VCC
CLK
nCLK
CLK_SEL
PCLK
nPCLK
VEE
CLK_EN
1
24
2
23
3
22
4 ICS8531-01 21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
VCCO
Q3
nQ3
Q4
nQ4
Q5
nQ5
VCCO
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
IDT™ / ICS™ 1-TO-9, 3.3V LVPECL FANOUT BUFFER
1
ICS8531AY-01 REV. F APRIL 11, 2007