IDT71024S70 View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
MFG CO.
'IDT71024S70' PDF : 7 Pages View PDF
IDT71024S70
CMOS STATIC RAM 1MEG (128K x 8-BIT)
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
ADDRESS
t RC
t AA
OE
CS1
t OE
t OLZ (5)
COMMERCIAL TEMPERATURE RANGE
CS2
DATA OUT
Vcc
Icc
SUPPLY
CURRENT
Isb
t ACS(3)
t CLZ (5)
HIGH IMPEDANCE
t PU
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
ADDRESS
DATAOUT
tRC
tAA
tOH
PREVIOUS DATAOUT VALID
t OHZ (5)
t CHZ (5)
DATAOUT VALID
t PD
3568 drw 05
tOH
DATAOUT VALID
3568 drw 06
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS1 is LOW, CS2 is HIGH.
3. Address must be valid prior to or coincident with the later of CS1 transition LOW and CS2 transition HIGH; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
5
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