IDTCV122C View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
MFG CO.
'IDTCV122C' PDF : 19 Pages View PDF
IDTCV122C
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PD, POWER DOWN
PD is an asynchronous active low input used to shut off all clocks cleanly prior to clock power. When PD is asserted low all clocks will be driven low before
turning off the VCO. In PD de-assertion all clocks will start without glitches.
PWRDWN
0
1
CPU
Normal
IREF * 2 or float
CPU#
Normal
Float
SRC
Normal
IREF * 2 or float
SRC#
Normal
Float
PCIF/PCI
33MHz
Low
USB
48MHz
Low
DOT96
Normal
IREF * 2 or float
DOT96#
Normal
Float
REF
14.318MHz
Low
PD ASSERTION
PD should be sampled low by two consecutive CPU# rising edges before stopping clocks. All single-ended clocks will be held low on their next high to low
transition. All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register determining to drive mode
is set to ‘tri-state’, the differential pair will be stopped in tri-state mode, undriven. When the drive mode but corresponding to the CPU or SRC clock of interest
is set to ‘0’ the true clock will be driven high at 2 x IREF and the complementary clock will be tristated. If the control register is programmed to ‘1’ both clocks will
be tristated.
PWRDWN
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
17
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