IR3Y48M View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'IR3Y48M' PDF : 31 Pages View PDF
IR3Y48M
Switching Characteristics
(AVDD, DVDD = 2.7 to 3.6 V, AVSS, DVSS = 0 V, TOPR = –30 to +85 ˚C, CL < 10 pF)
PARAMETER
SYMBOL
CONDITIONS
MIN. TYP. MAX. UNIT NOTE
Conversion speed
fS
0.5
20 MHz
Clock cycle period
tCYC
50
ns
Clock rise time
tR
(30%/70%) AVDD, DVDD
2
ns
Clock fall time
tF
(70%/30%) AVDD, DVDD
2
ns
Clock low period
tL
23
ns
Clock high period
tH
23
ns
Min. reference pulse
tWR
10
ns
Min. data pulse
tWD
10
ns
Reference sampling delay
tDR
4
ns
Data sampling delay
tDD
4
ns
Reference pulse setup
tSUR
–3
ns
1
Data pulse setup
tSUD
–3
ns
2
Reference pulse hold
tHR
5
ns
Data pulse hold
tHD
5
ns
Enable pulse setup
tSUE
10
ns
Enable pulse hold
tHE
10
ns
Tristate disable delay
tDLD Active/High-Z
20
ns
Tristate enable delay
tDLE High-Z/Active
20
ns
tDL1
ADC output data delay
tDL2
2
ns
35
ns
NOTES :
1. When SHR› is earlier than ADCKfi, assumed positive.
(In the above table, SHR› can be delayed a maximum of 3 ns behind ADCKfi.)
2. When SHD› is earlier than ADCK›, assumed positive.
(In the above table, SHD› can be delayed a maximum of 3 ns behind ADCK›.)
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