IR3Y48M View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'IR3Y48M' PDF : 31 Pages View PDF
IR3Y48M
[When ADCK Inverted by Register]
ADCK
ADC Input
N
N+1
Sampling Point
Digital Output
N–6
N–5
N+4
tDL1
N+5
0.7AVDD
0.3AVDD
N+6
6.0 clk
delay
N–2
tDL2
N–1
0.7DVDD
N
0.3DVDD
NOTE : At default condition of ADIN mode, falling edge of sampling and rising edge of data out are selected. If each edge
should be a rising edge, invert the ADCK by register setting. (The figure shown on the previous page is the default, the
following is the inverted one.)
Clock Waveform
tH
0.7AVDD
0.3AVDD
tR
tF
tL
tCYC
27
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