IR3Y48M View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'IR3Y48M' PDF : 31 Pages View PDF
CDS Circuit
CDS circuit holds CCD precharge (reference) level
at SHR pulse, then it samples CCD pixel data at
SHD pulse. Correlated (common) noise is removed
by subtraction of precharge level from pixel data
level.
IR3Y48M
CDS has the gain of maximum 12 dB (6 dB/step).
This gain is a part of total gain and it is controlled
by register value similar to gain in AGC circuit.
Connect signal from CCD sensor to CCDIN pin
through C-coupling. Place the same capacitor
between REFIN and AVSS.
Reference Clock (SHR)
Data Clock (SHD)
REFIN
CCD
CCDIN
CDS
CDS Output
= V (CDS)
= V (DAT) – V (PREC)
Reset
Pulse
CDS Operation
Reset
Pulse
V (PREC)
V (CDS) V (DAT)
SHR
SHD
SHR
SHD
SIG
SIG
fSMAX = 20 MHz/tSMIN = 50 ns
MAX. Level
7
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