ISPGDX2-256 View Datasheet(PDF) - Lattice Semiconductor
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Description
MFG CO.
'ISPGDX2-256' PDF : 72 Pages View PDF
Lattice Semiconductor
ispGDX2 Family Data Sheet
Sample External Timing Calculations
The following equations illustrate the task of determining the timing through the ispGDX2 family. These are only a
sample of equations to calculate the timing through the ispGDX2.
Figure 18 shows the specific delay paths and the Internal Timing Parameters table provides the parameter values.
Note that the internal timing parameters are given for reference only and are not tested. The external timing param-
eters are tested and guaranteed for every device.
Data from global select pin to output pin:
tPD_SEL = tSEL_IN + tMUXSEL + tOPBYPASS + tBUF
Global clock to output:
tCO = tCLK_IN + tGCLK + tOPCOi + tBUF
Input register or latch set-up time before global clock:
tIPS = tIN + tIPS - (tCLK + tGCLK)
Input register or latch hold time after global clock:
tIPH = (tCLK_IN + tGCLK) + tIPHi - tIN
Data from product term select to output pin:
tPD_PTSEL = tIN + tIPBYPASS + tROUTEGRP + tPTSEL + tMUXSEL + tOPBYPASS + tBUF
Product term clock to output:
tCO_PT = tIN + tIPBYPASS + tROUTEGRP + tPTCLK + tOPCOi + tBUF
Input register or latch set-up time before product term clock:
tIPS_PT = tIN + tIPSi_PT - (tIN + tIPBYPASS + tROUTEGRP + tPTCLK)
Input register or latch hold time after product term clock:
tIPH_PT = (tIN + tIPBYPASS + tROUTEGRP + tPTCLK) + tIPHi - tIN
Global OE input to output enable/disable:
tGOE/DIS = tGOE_IN + tOEBYPASS + tEN
External reset pin to output delay:
tOPRSTO = tSR_IN + tOPASROi + tBUF
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