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ISPGDX2-256 View Datasheet(PDF) - Lattice Semiconductor

Part Name
Description
MFG CO.
ISPGDX2-256
Lattice
Lattice Semiconductor Lattice
'ISPGDX2-256' PDF : 72 Pages View PDF
Lattice Semiconductor
ispGDX2 Family Data Sheet
sysHSI Block Timing
Figure 22 provides a graphical representation of the SERDES receiver input requirements. It provides guidance on
a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N
input skew tolerance.
Figure 22. Receive Data Eye Diagram Template (Differential)
Bit Time
V THD
200 mV Differential
+/- 100 mV Single Ended
jt TH
eo SIN
jtTH
jtTH : Optimum Threshold Crossing Jitter
The data pattern eye opening at the receive end of a link is considered the ultimate measure of received signal
quality. Almost all detrimental characteristics of a transmit signal and the interconnection link design result in eye
closure. This combined with the eye-opening limitations of the line receiver can provide a good indication of a link’s
ability to transfer error-free data.
Signal jitter is of special interest to system designers. It is often the primary limiting characteristic of long digital
links and of systems with high noise level environments. An interesting characteristic of the clock and data recovery
(CDR) portion of the ispGDX2 SERDES receiver is its ability to filter incoming signal jitter that is below the clock
recovery PLL bandwidth. For signals with high levels of low frequency jitter, the receiver can detect incoming data
error free, with eye openings significantly less than that shown in Figure 22.
sysHSI Block AC Specifications
Operating Frequency Ranges
Symbol
Description
Mode
Test Condition
Min.
Max. Units
SS:CAL
50
200
MHz
fCLK
Reference Clock Frequency 10B12B
8B10B
33
67
MHz
40
80
MHz
SS:CAL
with eoSIN
400
8001
Mbps
fSIN2
Serial Input
10B12B
with eoSIN
400
8001
Mbps
8B10B
with eoSIN
400
8001
Mbps
fSOUT2
Serial Out
LVDS
CL = 5 pF, RL = 100 Ohms,
fCLK with no jitter
400
8001
Mbps
1. fSIN (8B/10B and 10B/12B) 800Mbps limit applicable only to the fastest speed grade. Limit is 700Mbps for the lower speed grade.
2. fSIN and fSOUT speeds are supported at VCC and VCCP at 1.7V to 1.9V for ispGDX2C devices.
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