ISPGDX2 View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
MFG CO.
'ISPGDX2' PDF : 72 Pages View PDF
Lattice Semiconductor
ispGDX2 Family Data Sheet
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
IIL, IIH1 Input or I/O Low Leakage
0 ≤ VIN ≤ (VCCO - 0.2V)
(VCCO - 0.2V) < VIN ≤ 3.6V
—
—
10
μA
—
—
30
μA
IIH3
Input High Leakage Current
3.6V < VIN ≤ 5.5V and
3.0V ≤ VCCO ≤ 3.6V
—
—
3
mA
IPU
I/O Active Pull-up Current
0 ≤ VIN ≤ 0.7 VCCO
-30
—
-150
μA
IPD
I/O Active Pull-down Current
VIL (MAX) ≤ VIN ≤ VIH (MAX)
30
—
150
μA
IBHLS Bus Hold Low Sustaining Current VIN = VIL (MAX)
30
—
—
μA
IBHHS Bus Hold High Sustaining Current VIN = 0.7 VCCO
-30
—
—
μA
IBHLO Bus Hold Low Overdrive Current 0 ≤ VIN ≤ VIH (MAX)
—
—
150
μA
IBHLH Bus Hold High Overdrive Current 0 ≤ VIN ≤ VIH (MAX)
—
—
-150
μA
VBHT Bus Hold Trip Points
VCCO * 0.35
—
VCCO * 0.65 V
C1
I/O Capacitance2
VCCO = 3.3V, 2.5V, 1.8V
—
—
8
pf
VCC = 1.8V, VIO = 0 to VIH (MAX)
—
—
C2
Clock Capacitance2
VCCO = 3.3V, 2.5V, 1.8V
—
—
6
pf
VCC = 1.8V, VIO = 0 to VIH (MAX)
—
—
C3
Global Input Capacitance2
VCCO = 3.3V, 2.5V, 1.8V
—
VCC = 1.8V, VIO = 0 to VIH (MAX)
—
6
—
pf
—
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not
measured with the output driver active. Bus maintenance circuits are disabled.
2. TA = 25°C, f = 1.0MHz.
3. 5V tolerant inputs and I/Os should be placed in banks where 3.0V ≤ VCCO ≤ 3.6V. The JTAG ports are not included for the 5V tolerant inter-
face.
Supply Current
Over Recommended Operating Conditions (ispGDX2-256)4
Symbol
Description
Power Pins Vcc (V)
Min.
Typ.
Max.
3.3
—
59.6
—
Core Logic Power Supply Current
2.5
—
58.7
—
ICC1,2
VCC
GPLL/sysHSI Logic Power Supply
Current
1.8
—
60.0
—
3.3
—
118.7
—
2.5
—
118.7
—
1.8
—
117.5
—
ICCP2
GPLL/sysHSI CSPLL Power
Supply Current
3.3
—
14.7
—
VCCP
2.5
—
14.7
—
1.8
—
17.4
—
3.3
—
35
—
ICCO3
Bank Power Supply Current
VCCO
2.5
—
35
—
1.8
—
25
—
3.3
—
1.5
—
ICCJ
JTAG Programming Current
VCCJ
2.5
—
1.0
—
1.8
—
800
—
1. 64-input switching frequency at 20 MHz, with one GRP fanout.
2. One GPLL with fVCO = 400 MHz and one sysHSI Block (two receivers and two transmitters) at 622 MHz data rate.
3. All 8-bank reference circuit currents, all I/Os in tristate, inputs held at valid logic levels, and bus maintenance circuits disabled.
4. TA = 25°C
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
23
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