ISPGDX2 View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
MFG CO.
'ISPGDX2' PDF : 72 Pages View PDF
Lattice Semiconductor
ispGDX2 Family Data Sheet
Timing Model
The task of determining the timing through the ispGDX2 family is relatively simple. The timing model provided in
Figure 18 shows the specific delay paths. Once the implementation of a given function is determined either con-
ceptually or from the software report file, the delay path of the function can easily be determined from the timing
model. The Lattice design tools report the timing delays based on the same timing model for a particular design.
Note that the internal timing parameters are given for reference only, and are not tested. The external timing param-
eters are tested and guaranteed for every device.
Figure 18. ispGDX2 Timing Model Diagram (I/O Cell)
TOE/
GOE
t TOE_IN
t GOE_IN
t IOI
TOE path
GOE path
from GRP
t PTOE
to sysHSI
(REFCLK)
to FIFO
(WE)
GCLK/
GCLKEN
GSR
GSEL
IN
tCLK_IN
tCLKEN_IN
tIOI
t GCLK
tPLtLP_LSLE_DCE_DLAEYLAY
t SR_IN
tIOI
to sysHSI/FIFO
(Global Reset)
from GRP
tPTSR
t SEL_IN
t IOI
from GRP
tPTSEL
from GRP
from GRP
t PTCLKEN
t PTCLK
to FIFO
(WCLK)
from Adjacent
Cells (Output)
t MUXPD
tMUXSEL
t OPAC
from Adjacent Cells
(Input)
t IPAC
from FIFO
(DOUT)
from sysHSI
(RECCLK, SYDT)
t FIFODATAOUT
t HSIOUT
from PLL
(PLL Output)
t IN
t IOI
t PLLOUT
t INDIO
to sysHSI/FIFO
(SIN, Control, DIN, I/O Reset, SSCLKIN)
t OEBYPASS
OE Reg.
D
Q
CE
from sysHSI
S/R
(SOUT)
from sysHSI/FIFO
(Flags)
t OPBYPASS
from sysHSI
(SSCLKOUT)
Output Reg.
D
Q
t HSISOUT
t HSIFIFOFLAG
t HSISSCLKOUT
CE
S/R
Input Reg.
S/R
CE
D
Q
tIPBYPASS
Output
Delays
t BUF
t EN
t DIS
t IOO
OUT
to sysHSI
(TXD)
to Adjacent Cells
(Output)
t ROUTEGRP
to GRP
to Adjacent Cells
(Input)
Italicized parameters are optional.
Model Version 1.6.7
to FIFO
(REN)
to FIFO
(RCLK)
29
Share Link: 
