Lattice Semiconductor
ispGDX2 Family Data Sheet
Signal Descriptions1 (Continued)
Signal Names
HSImA_TXDw, HSImB_ TXDw
HSImA_RXDw, HSImB_ RXDw
Source Synchronous Functions
SS_SCLKIN0P, SS_SCLKIN1P
SS_SCLKIN0N, SS_SCLKIN1N
SS_CLKOUT0N, SS_CLKOUT1P
SS_CLKOUT0N, SS_CLKOUT1N
CAL
1. m, w, x, y and z are variables.
2. Not on ispGDX2-64
Description
Internal Signal – Parallel data in bit w for sysHSI BLOCK m channel A, B.
Internal Signal – Parallel data out bit w for sysHSI BLOCK m channel A, B.
Input – Positive sense clock input for Source Synchronous group A, B.
Input – Negative (minus) sense clock input for Source Synchronous group A, B.
Output – Positive sense clock output for Source Synchronous group A, B.
Output – Negative (minus) sense clock output for Source Synchronous group A, B.
Input – Initiates source synchronous calibration sequence.
ispGDX2-64 Power Supply and NC Connections1
Signal
ispGDX2-64 (100-Ball fpBGA)2
VCC
VCCO0
VCCO1
VCCO2
VCCO3
VCCO4
VCCO5
VCCO6
VCCO7
VCCJ
VCCP0
GNDP0
GND
A1, K10
J7
F10
E10
B7
B4
E1
F1
K4
K1
G6
G5
A10, B9, C8, E6, E5, F6, F5, H3, J2
1. All grounds must be electrically connected at the board level.
2. Pin orientation A1 starts from the upper left corner of the top
side view with alphabetical order ascending vertically and
numerical order ascending horizontally.
51