ISPGDX2 View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
MFG CO.
'ISPGDX2' PDF : 72 Pages View PDF
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-64 Logic Signal Connections (Continued)
Signal Name
sysIO LVDS
GDX
SERDES Mode
Bank Pair/Polarity Block MRB
I/O Pin1
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
100
fpBGA
GND
7
-
-
-
-
-
-
GND
BK7_IO6
7
31P
1B 14 HSI1B_CDRRSTb
-
FIFO3_FIFORSTb
K5
BK7_IO7/PLL_LOCK2
7
31N
1B 15
-
-
FIFO3_FULL
J5
GOE1
7
-
-
-
-
-
-
H5
1. The signals in this column route to/from the assigned pins of the associated I/O cell.
2. The signals in this column use the I/O cell. If a receiver signal is present in the I/O cell, the associated pin is available for output only. When
transmit data (TXD) is present in the cell, the associated pin is available for input only.
3. The DOUT outputs are routed to GRP through the input register of the cell and the DIN inputs are routed direct from the associated pins in
FIFO only mode. In SERDES with FIFO mode, the FULL and EMPTY flags are routed to the associated pins through the output MUX and
the pins.
4. If the Source Synchronous Receiver is used in the HSI Block, this pin is unavailable for another use and must be left unconnected.
5. The SYDT signal has two routing options. If direct output through the dedicated pin is used, the I/O cell (the whole HSI Block) is not avail-
able for transmitter. The SYDT in the I/O Cell column is routed to the GRP through the input register of the cell and frees the I/O cell for
transmitter.
6. FIFO_STRDb flag output is used in SERDES with FIFO Mode only.
7. sysHSI Source Synchronous Receive Mode is not available for channel 1A.
55
Share Link: 
