IT8673F View Datasheet(PDF) - ITE Tech. INC.
Part Name
Description
MFG CO.
'IT8673F' PDF : 128 Pages View PDF
IT8673F
LDN
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
Table 10-9. GPIO & Alternate Function Configuration Registers (cont’d)
Index R/W Reset
Configuration Register or Action
F5h R/W
00h
Simple I/O Enable Register
F6h R/W
00h
Simple I/O Direction Selection Register
F7h R/W
00h
Panel Button De-bounce Enable Register
F8h R/W
00h
Panel Button De-bounce Control Register / GP LED Blinking 2
Control Register
F9h R/W
00h
Keyboard Lock Pin Mapping Register
FAh R/W
00h
GP LED Blinking 1 Pin Mapping Register
FBh R/W
00h
GP LED Blinking Control & RING# Pin Mapping Register
FCh R/W
00h
GP LED Blinking 2 Pin Mapping Register
FDh R/W
00h
Reserved Register
FEh R/W
00h
PCI CLKRUN# Pin Mapping Register
FFh R/W
00h
SMI# Pin Mapping Register
E0h R/W
00h
SMI# Control Register 1
E1h R/W
00h
SMI# Control Register 2
E2h
R
00h
SMI# Status Register 1
E3h R-R/W 00h
SMI# Status Register 2
Notes:
*1: All these registers can be read from all LDNs.
*2: When the ECP mode is not enabled, this register is read only as “04h”, and cannot be written.
*3: When bit 2 of the base address of Parallel Port is set to 1, the EPP mode cannot be enabled. Bit 0 of this register is
always 0.
*4: The initial value of the activate bit of KBC is determined by the latched state of DTR2# at the falling edge of the RESET
signal.
*5: These registers are read only unless the write enable bit (Index=F0h) is asserted.
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